Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 51)

CAN 0 Interrupt Register (C0IR)
High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
51
7 6 5 4 3 2 1 0
SFR A5h INTIN7 INTIN6 INTIN5 INTIN4 INTIN3 INTIN2 INTIN1 INTIN0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
This SFR is not present on the DS80C411.
INTIN7–0
Bits 7–0 CAN 0 interrupt indicator 7–0. The C0IR register indicates the status of the interrupt sources bits in the
CAN 0 processor. The contents of C0IR indicate that no interrupt is pending (00 hex), if an interrupt is
due to a change in the CAN 0 status register (01 hex) or if an interrupt has been generated from the suc-
cessful reception or transmission of one of the 15 message centers (02–10 hex). The C0IR register is
cleared to 00 hex following a reset.
To properly reflect the value of each interrupt source in the C0IR register, each source must be enabled
by the respective interrupt enable. These include ERIE and/or STIE enable in the case of status-change-
related interrupt (01) sources and either the ETI or ERI enable for each message center interrupt (02–10
hex) source. The status values of the interrupt sources in C0IR do not, however, require setting either
the EA or C0IE bits in the IE and EIE SFR registers.
There are two methods for verifying message center interrupts. One method uses the ETI/ERI interrupt
enable in the CAN status register, and the other method uses the STIE interrupt enables within each CAN
message control register.
STIE = 1. When a transmission or a reception by the corresponding message center was successfully
completed, the status-change interrupt and the RXS/TXS bit are asserted. To understand how each bit
in the status register acts as an interrupt source, review the descriptions of each bit in the status regis-
ter. Note that a successful receive in relation to the RXS bit is dependent on the AUTOB bit (AUTOB =
1 is successful receive only, and AUTOB = 0 is successful receive and store). This is not the case with
the following ERI relationship, in which a receive is considered successful only if the data was stored in
the respective message center. The STIE interrupt method requires the microcontroller to poll each mes-
sage center to establish the respective interrupt source following each status-change interrupt.
ETI = 1 and/or ERI = 1. When a successful transmission or a successful reception and store by the cor-
responding message center are completed, the interrupt is asserted according to its priority. This
method relies on the hardwired priority of the message centers. Minimal microcontroller intervention is
required.
Terms used in the following description:
Value A is the value that was indicated before and is not zero.
MCV (message center’s value) is the interrupt indicator value, which corresponds to the message cen-
ter that received or transmitted a message (i.e., 02 for MC15, 03 for MC1, etc.).
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