Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 46)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
46
CRST
Bit 3
AUTOB
Bit 2
low-power mode. Setting SIESTA does not alter any CAN block controls or error status relationships.
Note that the PDE and SIESTA bits act independent of each other. Setting both bits leaves the CAN
processor in a low-power state until both bits have been cleared by their respective mechanisms.
CAN 0 reset. (Requires a timed-access write.) When CRST is set to a 1 and after completion of the last
reception, transmission, or after arbitration was lost or an error condition occurred, all CAN registers
located in the SFR memory map, with the exception of the CAN 0 control register are cleared to a 00
hex. The CAN 0 control register is set to 09 hex. Note that the term ‘after arbitration lost’ denotes the fact
the arbitration was lost and the reception following this lost arbitration is completed. Recall that the CAN
processor immediately becomes a receiver after it has lost its arbitration on the CAN bus. In accordance
with waiting until after the completion of the last reception, transmission, or after arbitration was lost or
an error condition occurred, a read of the CRST bit, when previously programmed to a 1, returns a 0,
until such time that the CRST = 1 state is actually allowed to place the CAN processor into the reset
state. As such, a read of the CRST bit verifies when the CAN reset has been engaged or removed. CAN
registers located in the MOVX memory map are left in the last state prior to setting CRST. Setting CRST
also clears both the receive- and transmit-error counters in the CAN controllers and sets the SWINT bit
to a 1. CRST must be cleared by software to remove the CAN reset and allow the CAN 0 processor to
be initialized. When the CAN processor is not in a bus-off mode (BSS = 0) and the CAN processor exits
either the software initialization mode (SWINT programmed from a 1 to a 0) or when the CAN reset is
removed (CRST bit is cleared from a 1 to a 0 and the SWINT bit is cleared from 1 to 0), the CAN proces-
sor performs a power-up sequence of 11 consecutive recessive bits before the CAN controller enters
into normal operation. If the CAN reset is removed and SWINT is left in the software initialization state,
the microcontroller is allowed to immediately start programming the CAN registers and MOVX data
memory prior to the completion of the power-up sequence. Exiting the software initialization mode
(SWINT ≥ 0) requires a power-up sequence of 11 consecutive recessive bits before the CAN controller
enters into normal operation. Clearing CRST to a 0 from a previous 0 state does not alter CAN proces-
sor operation. All writes to the CRST bit require a timed-access function.
Autobaud. When AUTOB is set to a 1, an internal loopback is enabled to AND the data from the exter-
nal CAN bus with the transmitted data of the CAN 0 processor. The “ANDed’ data is then connected to
the internal input of the CAN 0 processor. At the same time, the transmitted data is disabled from reach-
ing the external C0TX pin. The C0TX pin is placed into a recessive state when AUTOB = 1. The pur-
pose of the internal loopback and the disabled C0TX pin is to allow the CAN processor to establish the
proper CAN bus timing without disrupting the normal data flow between other nodes on the CAN bus.
Disabling the C0TX pin and setting the C0TX pin to a recessive state prevents the CAN processor from
driving nonsynchronized data onto the CAN bus (creating CAN bus errors to other nodes) when being
programmed with various frequencies to synchronize the processor with the CAN bus. With AUTOB =
1, the microcontroller autobaud algorithm makes use of the CAN 0 status register RXS and error status
bits to determine when a message is successfully received (when AUTOB = 1, a successful receive, a
store is not required). Each successive baud-rate attempt is proceeded by the microcontroller clearing
the transmit- and receive-error counters by a write of 00 to the transmit-error SFR register and a read of
the CAN 0 status register to clear the previous status-change interrupt. Note that a write to the transmit-
error SFR register automatically resets the CAN fault confinement state machine to an initial (error-active)
state if the error counters are cleared to 00 hex. If, however, the error counters are programmed to a
value greater than 128, the CAN processor is in an error-passive state. Appropriate flags are set when
the error counter is written with any value. A write of the status register is also used to remove the pre-
vious error value in the ER2–ER0 bits. Clearing the error counters also clears the EC96 bit, if set. When
BSS = 1, the CAN processor locks out the ability for the microcontroller to write to the error counters by
virtue of the fact that the SWINT bit is also forced to a 0 state during the period that the CAN processor
performs a bus recovery and power-up sequence. Once the CAN processor has removed itself from the
bus-off condition, it also clears BSS = 0, sets SWINT = 1, and clears both the transmit- and receive-error
counters to 00 hex. Imagine a system with only two nodes on the CAN bus.
The following two situations are examples of how the autobaud function works on the CAN processor. In
the first case, consider three nodes, A, B, and C, with nodes A and B operating in the normal CAN oper-
ational mode (nonautobaud) and node C (a DS80C400 CAN processor) attempting to establish a prop-
er baud rate using the autobaud features. If node A transmits a message, node B acknowledges this
message, and node C also receives the acknowledged message if it has the same baud rate. If node C
does not have the same baud rate as nodes A and B, node C detects the mismatch by the respective
error count. Node C then proceeds to adapt its baud rate and attempt to receive the following message.
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