Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 184)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
184
TRANSMIT/RECEIVE DATA BUFFER WORD ORIENTATION: ENDIANESS
The big/little-endian (BLE) bit of the MAC control (00h) CSR register defines the endianess with which the MAC handles each 32-bit
word transaction made by the BCU to/from the 8kB data buffer memory. The BLE bit defaults to 0, causing the MAC to consider each
32-bit word to be represented in little-endian byte order. If BLE is set to 1, the MAC considers each 32-bit word to be represented in
big-endian byte order. The endianess defined by the BLE bit applies to all word transactions made by the BCU between the MAC and
buffer memory, including transmit and receive status words reports made to the respective data buffers. Since the DS80C400 CPU can
only access the data buffer memory one byte at a time using the MOVX operation, little-endian byte ordering (BLE = 0) generally allows
for the most efficient buffer handling routines by the CPU. The following figure illustrates the two endian alternatives.
Figure 22-11. Big/Little-Endian Data Buffers
TRANSMITTING DATA
To transmit data over the MII or ENDEC interface, the CPU needs only to load the data buffer, supply size, and location of the buffer
and submit a transmit request to the buffer control unit (BCU) of the Ethernet controller. Data buffer memory should first be loaded with
the desired transmit data. After the data buffer has been loaded, the BCUD (E6h) and BCUC (E7h) SFR pair are used to communicate
size/location information and submit a transmit request to the BCU. The BCUD SFR needs to be written with the following information
about the data to be transmitted, in the following order: 1) MSByte of the length of the data, 2) LSByte of the length of data, and 3)
starting page for the data. Once this information has been written, the buffer command BC3:0 bits of the BCUC register can be writ-
ten with one of the three possible transmit requests: 0100b = normal, 0101b = disable automatic padding, or 0110b = disable FCS
field generation. Once the transmit request is submitted to the BCU, additional transmit requests submitted by writes to the BCUD and
BCUC registers are intentionally ignored (dropped) by the BCU until the current transmission completes or aborts. Data buffer memo-
ry remains accessible during transmission so that additional transmit/receive data buffers can be loaded or unloaded. When the trans-
mission has completed or has been aborted, the BCU returns a transmit status word for the given data buffer in the first word (32 bits)
of the starting page originally specified for the buffer. The transmit interrupt flag (TIF) is set after the transmit status word has been writ-
ten and an interrupt request to the CPU is generated, if the Ethernet activity interrupt source is enabled. A simple flow diagram for the
transmit process is provided in Figure 22-12.
Desired TX Buffer:
Dest Addr = 00-A0-00-01-02-03
Src Addr = 00-60-35-11-22-33
Length/type = 08 00
Data = 45 00 00 29 DB FB …….
.
.
Transmit status word
00 A0 00 01
02 03 00 60
35 11 22 33
08 00 45 00
00 29 DB FB
MAC
transmit
order
.
.
Transmit status word
01 00 A0 00
60 00 03 02
33 22 11 35
00 45 00 08
FB DB 29 00
MAC
transmit
order
LITTLE ENDIAN
(BLE = 0)
BIG ENDIAN
(BLE = 1)
Ascending address Ascending address
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