Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 182)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
182
One way to prevent receive packets from always being stored to the receive data buffer, and thus prevent needless interruption of the
CPU, is to use the flush filter failed-packet enable function. The flush filter failed-packet enable (FPE: EBS.7) bit of the EBS SFR is pro-
vided as a simple means to automatically manage consumption of the receive data buffer. The FPE bit enables the BCU to flush a
receive packet as soon as it fails the destination address filter. Setting the FPE bit to 1 causes the BCU to ignore any receive data once
the destination address filter has failed. Thus, no pages in the receive data buffer are consumed, the receive FIFO is not updated, and
the CPU is not interrupted. Note that the promiscuous mode (PM = 1) results in the FF bit always being returned clear (= 0), effective-
ly disabling the flush filter packet enable function. Setting the receive all (RA) bit of the MAC control CSR register to 1 overrides the
FPE bit but allows the FF bit to be set according to the current destination address filter. Clearing the FPE bit to 0 results in the BCU
receiving all incoming packets into the receive buffer, regardless of the destination address filter.
USING THE HASH TABLE
The MAC control (00h) CSR register contains two bits, hash only (HO, bit 15) and hash/perfect (HP, bit 13), that can be configured to
initiate hash filtering of destination addresses. These two filter mode control bits and the resulting address filtering mode are described
in the DS80C400 data sheet. Once hash filtering has been selected, the destination address is passed through the CRC-32 generator
circuitry in order to produce an index into the hash table formed by the multicast address high (0Ch) and multicast address low (10h)
CSR registers. The most significant bit of the resultant CRC-32 is used to select one of the two CSR registers just mentioned. The next
five most significant bits are used to select one of 32 programmable bits in the respective CSR register. If the selected bit per the 6-
bit indexing process just described is set to 1, the destination address passes the hash address filter. If the indexed bit is 0, the des-
tination address fails the hash address filter. Remember that each bit in the hash table corresponds to many addresses, so the appli-
cation must perform additional checking in order to make sure that the address matches with one that it wants to pass.
VLAN SUPPORT
The DS80C400 supports one-level and two-level tagged VLAN frames. A VLAN-tagged frame contains a tag protocol ID (TPID) in the
13th and 14th bytes (those bytes normally occupied by the type/length field). These 2 bytes are compared to the values programmed
in the VLAN1 (20h) and VLAN2 (24h) CSR registers. If a nonzero match occurs with the VLAN1 register, the maximum frame length is
extended by four bytes: two bytes for the TPID already received and 2 bytes for the tag control information that immediately follows the
TPID. If the 13th and 14th bytes match the VLAN2 register settings, the maximum frame length is extended by 20 bytes: 2 bytes for
the TPID already received and 18 bytes for any tag control information. The DS80C400 data sheet diagrams the VLAN1 and VLAN2
tagged frames. The absolute requirements for virtual LAN implementations are not rigidly defined by IEEE, thus the DS80C400’s VLAN1
and VLAN2 register options provide the system administrator with the flexibility to accommodate different VLAN schemes.
PARTITIONING THE 8kB ETHERNET DATA BUFFER MEMORY
An on-chip 8kB SRAM is provided for Ethernet transmit/receive data packet buffering. The address location of this 8kB data memory
is determined by the setting of the IDM1:0 bits of the MCON (C6h) SFR. The 8kB data buffer memory is logically configured as 32 256-
byte pages. These 32 pages are partitioned between receive and transmit data buffer memory per the setting of the buffer size (BS4:0)
bits of the EBS (E5h) SFR. The BS4:0 bits can be programmed to any value n between 0 and 31, inclusive. The receive buffer occu-
pies the first n pages of the 8kB memory, while the transmit buffer occupies the remaining (32-n) pages. Changing the BS4:0 bits auto-
matically flushes the contents of the receive buffer and receive FIFO. The Ethernet buffer control unit directly accesses the 8kB data
buffer memory through its 32-bit wide datapath. The CPU must access the 8kB data buffer memory one byte at a time using MOVX
instructions. Each of the data buffers, receive and transmit, operate in a circular fashion. The following is a diagram showing how one
could partition the 8kB buffer memory for 8 receive pages and 24 transmit pages.
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