Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 86)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
86
7 6 5 4 3 2 1 0
SFR E7h BUSY EPMF TIF RIF BC3 BC2 BC1 BC0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Buffer Control Unit Control (BCUC)
R = Read returns page information of the first packet in the receive FIFO, W = Unrestricted write, -n = Value after reset
BUSY
Bit 7
EPMF
Bit 6
TIF
Bit 5
RIF
Bit 4
BC3-0
Bits 3-0
Busy. This read-only busy indicator is set by the hardware when the BCU is in the process of executing
a CSR read/write operation. It is cleared by the BCU when it is done. Data writes to this bit are ignored.
Ethernet power mode interrupt flag. This flag is set when the power-management block detects a
wake-up frame or a magic packet. Setting this flag causes an Ethernet power mode interrupt to be gen-
erated. This flag must be cleared by software once set. If this flag is set by software, an Ethernet power
mode interrupt is generated if enabled.
Transmit interrupt flag. This flag is set when the BCU has stored a transmit status word in the transmit
buffer after a packet transmission. Setting this flag causes an Ethernet activity interrupt to be generat-
ed if enabled. This flag must be cleared by software once set. If this flag is set by software, an Ethernet
activity interrupt is generated if enabled.
Receive interrupt flag. This flag is set by hardware when the BCU has stored a receive status word to
the receive buffer and updated the receive FIFO after it has received a packet from the MAC. This flag
is also set by an invalidate current frame command whenever the receive FIFO is not empty and the flag
is not currently set. Setting RIF causes an Ethernet activity interrupt to be generated if enabled. This flag
is cleared by hardware whenever: 1) the receive FIFO becomes empty, 2) a BCU command empties the
receive buffer (invalidating the only packet or flushing buffer), 3) the EBS register is updated to change
the size of the buffers, or 4) a reset condition occurs. Otherwise, this flag must be cleared by software
once set. If this flag is set by software, an Ethernet activity interrupt is generated if enabled. Note that
there is potential of missing an interrupt when RIF is cleared immediately following an invalidate current
frame command if there is another frame in the receive buffer. It is recommended to clear the flag before
invalidation.
BCUC control bits. These bits are used as the BCU command bits to provide communication between
the BCU and CPU. The following BCU commands are supported. All other BC3:0 command values are
reserved and are ignored by the BCU.
BCUC3:BCUC0 COMMANDS
0000 No operation (default)
0010 Invalidate current receive packet
0011 Flush receive buffer
0100 Transmit request—Normal
0101 Transmit request—Disable padding
0101 Transmit request—Add CRC disabled
1000 Write CSR
1001 Read CSR
1100 Enable sleep mode
1101 Disable sleep mode
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