Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 177)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
177
For reception, the MAC automatically synchronizes on the preamble and start-of-frame delimiter bytes. The MAC distinguishes among
broadcast, multicast, and unicast frames. The MAC performs automatic minimum/maximum frame length and FCS checking on incom-
ing frames. The MAC interprets the type/length field for each frame and can extend the maximum frame length for VLAN1-tagged and
VLAN2-tagged frames. The MAC can optionally be configured to strip zero-padding and FCS information before receive packet data
is transferred (by the BCU) to data buffer memory. Additionally, the MAC can detect unsupported control frames, dribbling bit errors,
runt frames, and any other errors signaled by the RX_ER input from the PHY. Bit 30 of the receive status word, the packet filter (PF) bit,
serves as an indication of whether the MAC detected any errors in the receive frame. The receive status word contains other status
bits such that the application can further discern what type of error was detected. One exception to this generalization is when the dis-
able broadcast frames (DBF) bit of the MAC control register has been set to 1. When broadcast frames have been disabled (DBF =
1), the PF bit is returned as 0 in the receive status word for any broadcast frame received.
USING THE MII SERIAL MANAGEMENT BUS
The DS80C400 provides a 2-wire, serial MII management interface for communication with external PHY devices. This interface is com-
prised of the MDC clock signal and the bidirectional MDIO data line. The MDC clock rate is derived from the system clock frequency,
and data is valid on the rising edge of the clock (MDC). The AC timing section of the DS80C400 data sheet contains detailed timing
information relative to the MDC, MDIO signals. The MII management frame format, as defined by clause 22 of the IEEE 802.3 standard,
is shown in Figure 22-6. The CSR registers MII address (14h) and MII data (18h) allow the CPU to execute read/write operations over
the two-wire serial bus. The MII address register supports a 5-bit address field and 5-bit register pointer field and therefore can address
up to 32 registers in as many as 32 PHY devices. The MII data register holds the returned 16-bit data following a read operation and
should be loaded with the desired 16-bit data prior to a write operation. The MII serial management bus operates identically for full-
duplex MII, half-duplex MII, and serial ENDEC mode.
HALF-DUPLEX OPERATION–CSMA/CD AND FLOW CONTROL
The CSMA/CD protocol specifies that each Ethernet station must wait until there is no signal on the channel. Then it can begin trans-
mitting. If there is a signal (carrier) on the channel, all other stations must wait until carrier ceases before trying to transmit. The proto-
col supports multiple accesses, allowing all Ethernet stations the equal ability to send frames onto the network. Because signals take
a finite time to travel from one end of an Ethernet system to the other, the first bits of a transmitted frame do not reach all parts of the
network simultaneously. Therefore, it is possible for more than one station to sense that the network is idle and to start transmitting their
frames simultaneously. When this happens, the Ethernet system has to be able to sense the “collision” of signals, stop the transmis-
sion, and resend the frame.
The CSMA/CD protocol is designed to provide fair access to the shared channel so that all stations get a chance to use the network.
After every packet transmission, all stations use the CSMA/CD protocol to determine which station gets to use the Ethernet channel
next. A collision occurs if more than one station transmits on the Ethernet channel at the same moment. The stations are notified of this
event, and instantly reschedule their transmission using a specially designed back-off algorithm. As part of this algorithm, the stations
involved choose a random time interval to schedule the retransmission of the frame, which keeps the nodes from making retransmis-
sion attempts simultaneously. Collisions are normal and expected events on an Ethernet. As more stations are added to a given
Ethernet and as the traffic level increases, more collisions occur as part of the normal operation of an Ethernet. A normal collision does
not result in lost data. In the event of a collision, the Ethernet interface backs off for microseconds and then automatically retransmits
the data. On a network with heavy traffic loads, multiple collisions can occur for a given frame transmission attempt. If repeated colli-
sions occur for a given transmission attempt, then the stations involved begin expanding the set of potential back-off times (truncated
binary exponential back-off), from which they choose their random retransmission time. This provides an automatic method for Ethernet
controllers to adjust to traffic conditions on the network. Only after 16 consecutive collisions for a given transmission attempt does the sta-
tion finally discard the Ethernet packet. This can happen only if the Ethernet channel is overloaded for long period of time or is broken in
some way.
Preamble
(32 bits)
Start
(2 bits)
Op code
(2 bits)
PHY Address
(5 bits)
PHY Register
(5 bits)
Turn Around
(2 bits)
Data
(16 bits)
Idle
(1 bit)
Read 111…111 01 10 PHYA [4:0] PHYR[4:0] ZZ* ZZ….ZZ* Z
Write 111…111 01 01 PHYA [4:0] PHYR[4:0] 10 PHYD[15:0] Z
* During a read operation, the external PHY drives the MDIO line low for the second bit of the turnaround field to indicate proper
synchronization and then drives the 16 bits of read data requested.
Figure 22-6. MII Management Frame Format
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