Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement User Manual
Page 131
High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
131
The DS80C400 supports interrupts from any location in the 24-bit address field. When an interrupt request is acknowledged, the cur-
rent contents of the 24-bit program counter (PC) are pushed onto the stack, and the page value (00h) and the lower 16-bit address of
the interrupt vector are then written to the PC before the execution of the hardware LCALL. This means that all interrupt vectors are
fetched from address 0000xxh, rather than the current page as defined by the AP register. The RETI instruction pops the three address
bytes from the stack and restores these bytes back to the PC at the conclusion of the interrupt service routine. Interrupt service rou-
tines that branch over page boundaries must save the current contents of AP before altering the AP register, as it is not automatically
saved on the stack. This mechanism supports up to three levels of nesting for interrupts.
One extra machine cycle is required to handle the additional byte associated with the extension to 24-bit addressing. The storage of the
24-bit address during an interrupt, LCALL, or ACALL instruction also requires three bytes of stack memory, as opposed to the tradition-
al two bytes in the 16-bit address mode. In this mode, the third byte of the PC (PC[23:16]) is not incremented when the lower 16 bits in
the lower two bytes of the PC (PC[15:0]) rolls over from FFFFh to 0000h. In the 24-bit paged address mode, PC[23:16] functions only as
a storage register, which is loaded by the address page (AP) register whenever the processor executes an ACALL, LCALL, or LJMP
instruction. PC[23:16] is stored and retrieved from the stack with the lower 16-bit of address in PC[15:0] when stack operation is required.
In paged address mode, MOVX instructions that utilize the data pointers (such as
MOVX @DPTR, A) form the 24-bit data address by
concatenating the contents of the currently selected extended DPTR register (DPX, DPX1, DPX2, or DPX3) with the contents of the
DPTR. The extended data pointer register values are not affected when the lower 16 bits of the selected DPTR overflows or underflows.
To maintain compatibility with existing 8051 compilers, the
JMP @A+DPTR and MOVC A, @A+DPTR instructions from 24-bit paged
address mode are limited to the current 64kB page, as specified by the upper 8 bits of the current instruction execution address reg-
ister. There is not a carry function into the contents of the extended data pointer register (DPX, DPX1, DPX2, or DPX3).
The modification of instructions in the 24-bit paged address mode is summarized in the following table.
INSTRUCTION CODE
MNEMONIC
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
HEX
BYTE
CYCLE
EXPLANATION
ACALL
addr11
a
10
a
7
a
9
a
6
a
8
a
5
1
a
4
0
a
3
0
a
2
0
a
1
1
a
0
Byte 1
Byte 2
2
4
(PC
15:0
) = (PC
15:0
) + 2
(SP) = (SP) + 1
((SP)) = (PC
7:0
)
(SP) = (SP) + 1
((SP)) = (PC
15-8
)
(SP) = (SP) + 1
((SP)) = (PC
23:16
)
(PC
10:0
) = addr11
(PC
23:16
) = (AP
7:0
)
LCALL
addr16
0
a
15
a
7
0
a
14
a
6
0
a
13
a
5
1
a
12
a
4
0
a
11
a
3
0
a
10
a
2
1
a
9
a
1
0
a
8
a
0
12
Byte 2
Byte 3
3
5
(PC
15:0
) = (PC
15:0
) + 3
(SP) = (SP) + 1
((SP)) = (PC
7:0
)
(SP) = (SP) + 1
((SP)) = (PC
15-8
)
(SP) = (SP) + 1
((SP)) = (PC
23:16
)
(PC) = addr16
(PC
23:16
) = (AP
7:0
)
LJMP
addr16
0
a
15
a
7
0
a
14
a
6
0
a
13
a
5
0
a
12
a
4
0
a
11
a
3
0
a
10
a
2
1
a
9
a
1
0
a
8
a
0
02
Byte 2
Byte 3
3
4
(PC) = addr16
(PC
23:16
) = (AP
7:0
)
RET
0
0
1
0
0
0
1
0
22
1
5
(PC
23:16
) = ((SP))
(SP) = (SP) - 1
(PC
15-8
) = ((SP))
(SP) = (SP) - 1
(PC
7:0
) = ((SP))
(SP) = (SP) - 1
RETI
0
0
1
1
0
0
1
0
32
1
5
(PC
23:16
) = ((SP))
(SP) = (SP) - 1
(PC
15-8
) = ((SP))
(SP) = (SP) - 1
(PC
7-0
) = ((SP))
(SP) = (SP) - 1
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