Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 173)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
173
Figure 22-1. Ethernet Controller Block Diagram
Assigning a Physical MAC Address
The 48-bit physical MAC address for the Ethernet controller is stored in the MAC address high (04h) and MAC address low (08h) CSR
registers. These on-chip registers are volatile memory locations and, following any reset, automatically default to a physical MAC
address of FF-FFFF-FF-FF-FF or the broadcast address.
An Ethernet-enabled system must be programmed with a unique MAC address, which can be acquired in several ways based on the
system software. Once a MAC address has been assigned to the network-enabled end product it is intended to be permanent.
If using the MxTNI™ runtime environment (programming in the JAVA language) or the NetBoot feature, the DS80C400/410/411 requires
an external MAC ID device as shown in the Table 22-1. The software automatically searches the 1-Wire bus during initialization, and if
the device is found, the guaranteed unique 48-bit serial number is read out and programmed into the MAC address CSR registers. If
a valid 48-bit serial number is not found, the Ethernet send/receive functions are disabled but the other features of the device are func-
tional. Details of the NetBoot procedure and a list of acceptable 1-Wire devices for holding the 48-bit physical MAC address are avail-
able in
Application Note 3398: DS80C400/DS80C410/DS80C411 Network Boot.
If the application code is written in the C language, user application code is responsible for programming the desired MAC address
directly into the CSR registers. The Maxim-supplied startup file (startup400.a51) for the Keil C compiler has options to set the MAC
address to a user-defined value, eliminating the need for an external MAC ID device.
Table 22-1. Source of MAC Addresses
Configuring the Mac Operational Mode
The media access controller works autonomously based upon the settings that have been programmed into various command/status
(CSR) registers. Table 22-2 summarizes the MAC control (00h) CSR register bits for full-duplex, half-duplex, and loopback modes of oper-
ation, ordering the bits according to function as related to PHY interface, address/packet filtering control, CSMA/CD functionality, and data
packet/buffer handling, respectively. Each mode of operation and associated function is covered in detail later in this section.
APPLICATION DS80C400 DS80C410/411
NetBoot DS2502-E48, DS2502P-E48
DS2502 or DS1982 (preprogrammed with
MAC ID), DS2502-E48, DS2502P-E48
MxTNI Runtime
Environment
DS2502 or DS1982 (preprogrammed with MAC ID),
DS2502-E48, DS2502P-E48
C Language
DS2502 or DS1982 (preprogrammed with MAC ID), DS2502-E48, DS2502P-E48
(or user-defined MAC ID via startup400.a51 file)
MII
MANAGEMENT
BLOCK
(Serial interface bus
to external PHYs)
MII I/O BLOCK
(Transmit, receive,
and flow control)
CSR REGISTERS
ADDRESS CHECK
BLOCK
POWER
MANAGEMENT
BLOCK
MAC HOST INTERFACE
BCU
TX/RX BUFFER
MEMORY
(8kB)
EXTERNAL
PHY(s)
80C400 ON-CHIP ETHERNET CONTROLLER
80C400
CPU
MxTNI is a trademark of Maxim Integrated Products, Inc.
Maxim Integrated