Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 79)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
79
7 6 5 4 3 2 1 0
SFR D6h IRAMD PRAME — — PDCE7 PDCE6 PDCE5 PDCE4
RT-* RT-* RT-1 RT-1 RT-0 RT-0 RT-0 RT-0
Multiplier C Register (MC)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
7 6 5 4 3 2 1 0
SFR D5h MC.7 MC.6 MC.5 MC.4 MC.3 MC.2 MC.1 MC.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
MC.7–0
Bits 7–0 Multiplier C register. The multiplier C register is also termed the accumulator register within the math
accelerator. Each time a multiply or divide is performed with the MA and MB registers, the resulting value
is added to the previous value of the accumulator and is then stored back into the accumulator. All shift
or normalization tasks are not added to the accumulator. The MC register is a full read/write register that
provides direct access to the accumulator. The accumulator is 40-bits long and is accessed by five
reads or writes of the MC register. The accumulator is cleared following a system reset, setting the CLMC
bit in the MCNT1 SFR, or by loading five consecutive 00 hex values into the MC register.
A read pointer and a write pointer keep track of which of the five bytes is read or written to when access-
ing or loading the 40 bits of the accumulator. The pointer is set to the most significant byte for reads and
the least significant byte for writes following a system reset, the completion of a calculation, the setting
of the CLM bit, or the setting of the MST bit in the MCNT1 SFR. Following each read of MC, the read
pointer is moved to the next less significant byte until the entire contents of MC are read. Similarly, each
write moves the write pointer to the next more significant byte until the entire 40 bits of the MC register
is written. Neither of the pointers wrap around but rather lock at the extreme end of the associated read
or write 40-bit word size. Note that, in loading or reading a 16-bit (or 32-bit) value, only two (or four)
reads or writes are required. In loading a 16-bit (or 32-bit) value, it is important to make sure that the
remaining 16 bits (or 8 bits) of the 40-bit value are all cleared.
The most significant byte is the first byte read from MC when downloading the contents of a completed
addition of the accumulator, as determined by the MST bit in the MCNT1 SFR. Unlike the MA and MB
registers, data in the accumulator is not cleared during a read. All subsequent reads of MB, after com-
pleting the appropriate reads to secure the respective results of the above calculations, produce the
contents of the fifth byte of data associated with the 40-bit accumulator value. When loading the MC reg-
ister, data must be written with the least significant byte first and most significant byte last.
Memory Control Register 1 (MCON1)
R = Unrestricted read, T = Timed-access write, -n = Value after reset, * = See bit description
IRAMD
Bit 7
PRAME
Bit 6
Bits 5, 4
Internal RAM Disable. IRAMD provides a software option to disable the 64kB internal SRAM. When
IRAMD is 0, the 64kB internal SRAM is active as data or merged program/data memory, dependent on
the logical state of the PRAME bit. When IRAMD is 1, the 64kB internal SRAM is disabled and removed
from the memory map. This bit affects the 64kB internal SRAM only; other internal data segments (the
8kB Ethernet buffer, the 1kB extended stack, and the 256 CAN buffer) are not affected. This bit is only
present on the DS80C410/411 and resets to 0. It is undefined on the DS80C400.
Program RAM Enable. PRAME provides a software selection to use the 64kB internal SRAM as merged
program and data memory. When PRAME is 0, the 64kB internal SRAM is used as data memory only.
When PRAME is 1, the 64kB internal SRAM is mapped to the lower 64kB program and data memory
spaces and functions as both program and data memory. This bit has no meaning when IRAMD is set
to logic 1 which disables the internal SRAM. This bit is only present on the DS80C410/411 and resets to
0. It is undefined on the DS80C400.
Reserved.
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