Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 41)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
41
Programming AM1 and AM0 to 10 or 11 enables the fully contiguous 24-bit program counter-address-
ing mode. In this mode, the processor addresses program memory with a full 24-bit program counter
(A23–A0) and does not utilize the AP register as an input to the program counter. AP is converted into
a general-purpose read/write SFR and does not have any relationship to the program counter or address
field. Note that AM1 and AM0 bits default to 00 on all resets, so the 24-bit contiguous address mode
must be enabled before executing the following four instructions:
1) MOV DPTR, #data24
2) ACALL addr19
3) LCALL addr24
4) LJMP addr24
C0TMA0.7–0
Bits 7-0
C0TMA0.7
Bit 7
C0TMA0.6
Bit 6
C0TMA0.5
Bit 5
C0TMA0.4
Bit 4
C0TMA0.3
Bit 3
C0TMA0.2
Bit 2
C0TMA0.1
Bit 1
C0TMA0.0
Bit 0
CAN 0 transmit message acknowledgment register 0. The C0TMA0 bits indicate which message cen-
ter (1–8) has successfully transmitted a message since the last read of the register. The contents of the
C0TMA0 register are updated each time a new message is successfully transmitted. The contents of the
C0TMA0 register are automatically cleared following each read of C0TMA0 by the microcontroller. A bit
value of 1 indicates that the assigned message center has been successfully transmitted since the last
read of the C0TMA0 register. A bit value of 0 indicates that no new message has been successfully
transmitted since the last read of the C0TMA0 register. Interrupts are not generated as a result of bits
being set in the C0TM0 register. This register works fully independent of the status bits in the CAN sta-
tus register, the INTIN7–0 vector in the CAN interrupt register, and the INTRQ bit in the CAN message
control registers.
Message center 8, message transmitted.
Message center 7, message transmitted.
Message center 6, message transmitted.
Message center 5, message transmitted.
Message center 4, message transmitted.
Message center 3, message transmitted.
Message center 2, message transmitted.
Message center 1, message transmitted.
CAN 0 Transmit Message Acknowledgment Register 0 (C0TMA0)
7 6 5 4 3 2 1 0
SFR 9Eh C0TMA0.7 C0TMA0.6 C0TMA0.5 C0TMA0.4 C0TMA0.3 C0TMA0.2 C0TMA0.1 C0TMA0.0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
R = Unrestricted read, -n = Value after reset. The C0TMA0 is cleared to 00h on all forms of reset, including the reset established by the CRST bit.
This SFR is not present on the DS80C411.
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