Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 47)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
47
ERCS
Bit 1
SWINT
Bit 0
In the second case, consider a system with only two nodes on the CAN bus. Consider node A in the
autobaud mode and the second node on the bus in the normal CAN operational mode. Node B trans-
mits a message and does not receive an acknowledgment, since there is no third node on the bus that
is also properly synchronized with the bus and in the normal CAN operational mode. Once node B
enters into an error-passive mode (after 16 repeated messages), it begins to send passive error flags.
Note that, when node B is operating in an error-passive mode, it does not send any dominant errors flags
to the bus. Once node A has established the proper baud rate, it receives the correct message. The
internal autobaud loopback path also allows the passive acknowledgment error sent by node B to be
“ANDed” with the dominant, internally transmitted acknowledgment bit from node A. As such, node A
sees no errors, which establishes the fact that it is properly synchronized with the bus. Node A now exits
out of the autobaud mode (AUTOB = 0) and enters into the normal CAN operational mode (with full
transmit capability to the CAN bus). In this mode, node A then acknowledges the next message from
node B.
Error count select. The ERCS bit establishes in which level the error counters set or clear the X96/128
bit in the CAN 0 status register. When ERCS = 0, the EC96/128 flag operates in an EC96 mode. In this
mode, the EC96/128 bit is set to a 1 whenever the error count of either the transmit- or receive-error
counters exceed 96. When ERCS = 1, the EC96/128 flag operates in an EC128 mode. In the EC128
mode, the EC96/128 flag is set to a 1 whenever the error count of either the transmit- or receive-error
counters reach a level of 128 or greater.
Software initialization. (Unrestricted read/write if BSS = 0, and read only if BSS = 1.) The SWINT bit
establishes the initialization state for CAN 0, which disables CAN 0 bus activity to allow the processor
to modify the MOVX SRAM assigned to the message centers without corrupting messages. When
SWINT is set to 1 and after completion of the last reception or transmission, after arbitration was lost, or
after an error condition occurred, all CAN 0 bus activity is disabled, allowing the processor to initialize
any or all of the CAN 0 MOVX SRAM. Note that the term ‘after arbitration lost’ denotes the fact the arbi-
tration was lost and the reception following this lost arbitration is completed. Recall that the CAN proces-
sor immediately becomes a receiver after it has lost its arbitration on the CAN bus. A read of the SWINT
bit verifies when the CAN processor software initialization mode has been engaged or removed.
Although the transmit- and receive-error counters are not cleared when the SWINT bit is set, the CAN 0
transmit- and receive-error counters can be altered by software through the use of the CAN 0 transmit-
error SFR register, as long as SWINT = 1. Setting SWINT to a 1 also clears the SIESTA bit independent
of what is stored to the SIESTA bit location during or prior to the write of the C0C register. Clearing SWINT
= 0 hardware also disables the microcontroller from writing to the first 16 bytes of the CAN MOVX mem-
ory. These 16 locations make up the CAN 0 control/status/mask registers. When SWINT = 0, the micro-
controller is allowed to write to any of the MOVX CAN register sites. All MOVX registers are readable at
any time, independent of the SWINT bit. Also note that the SWINT bit does not alter the read or write
access to any of the CAN 0 SFR registers or MOVX CAN message center registers. SWINT is pro-
grammed to a 0 when the processor has completed the MOVX SRAM initialization and CAN 0 bus activ-
ity has started. Software write access to the error counters is disabled when SWINT is cleared to a 0. A
bus-off condition is caused by a high number of errors on the CAN bus. When a bus-off condition
occurs, the CAN processor clears the SWINT bit to a 0 and immediately starts a bus recover and power-
up sequence. During this time, the microcontroller is limited to only reading this bit. All microcontroller
write access to SWINT is disabled when BSS = 1.
If the SWINT bit is set by a system reset, programming the CRST bit or setting the SWINT bit without the
prior detection of a bus-off condition can cause an adverse condition. Clearing SWINT by software
allows the CAN processor to synchronize itself to the CAN bus after the CAN processor executes a
power-up sequence (11 recessive bits). The power-up sequence requires the CAN processor to detect
11 consecutive recessive bits. (In CAN protocol, this is termed a power-up sequence.) When SWINT =
0 by a bus-off condition, bus off forces the CAN processor to initiate a standard bus-off recovery
sequence (128kB x 11 recessive bits). This is followed by entering into a reset state, requiring a power-
up sequence (11 recessive bits), after which the CAN processor enters into the idle state (normal oper-
ation, BSS = 0) and sets the SWINT bit to a 1. This bit is not intended for use in changing data within
the message centers after the CAN processor is placed into operation. Changes to the arbitration or
data fields in the message centers should be done through the use of the MSRDY bit in the respective
message (1–15) control registers. The SWINT bit is locked into the SWINT = 1 state until the bus timing
registers are programmed to valid states. (The invalid states are 00 hex. See the CAN bus timing regis-
ters in the CAN control/status/mask registers.)
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