Accumulator (ac), One’s complement adder data (ocad), Csr data (csrd) – Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement User Manual
Page 84: Csr address (csra), Accumulator (acc)
High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
84
7
6
5
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0
SFR E0h
ACC.7
ACC.6
ACC.5
ACC.4
ACC.3
ACC.2
ACC.1
ACC.0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
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6
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4
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1
0
SFR E1h
OCAD.7
OCAD.6
OCAD.5
OCAD.4
OCAD.3
OCAD.2
OCAD.1
OCAD.0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
7
6
5
4
3
2
1
0
SFR E3h
CSRD.7
CSRD.6
CSRD.5
CSRD.4
CSRD.3
CSRD.2
CSRD.1
CSRD.0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
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1
0
SFR E4h
CSRA.7
CSRA.6
CSRA.5
CSRA.4
CSRA.3
CSRA.2
CSRA.1
CSRA.0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
Accumulator (ACC)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
One’s Complement Adder Data (OCAD)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
CSR Data (CSRD)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
CSR Address (CSRA)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
ACC.7–0
Bits 7–0
Accumulator. This register serves as the accumulator for arithmetic operations. It is functionally identi-
cal to the accumulator found in the 80C32.
OCAD.7–0
Bits 7–0
One’s complement adder data. This register serves as the data register for the one’s complement
adder. Two writes to the OCAD initiate a summation by the one’s complement adder. When loading the
OCAD, data must be written with the least significant byte first and then the most significant byte. When
accessing data from the accumulator, the most significant byte is the first byte read from the OCAD. Four
reads are required to fully download the contents of the accumulator.
CSRD.7–0
Bits 7–0
CSR data. This register serves as the CSR data register for accessing CSR registers inside the MAC
core. For a CSR write operation, data to be written to a CSR register is loaded to the 32-bit CSR plat-
form register through the CSRD. Data is accessed by the CSRD after a CSR read operation.
CSRA.7–0
Bits 7–0
CSR address. This register serves as the CSR address register for accessing CSR registers inside the
MAC core. The lower 8-bit address of the desired CSR register is input through the CSRA to the BCU.
Maxim Integrated