Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 15)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
15
DeviceNet is a trademark of OpenDeviceNet Vendor Association Inc.
16 interrupt sources, 6 external and 10 internal with three levels of interrupt nesting and two programmable priority levels
Crash-proof, bandgap-referenced power-fail warning; voltage sense reset; and automatic power-up reset timeout
Programmable system clock divide control of crystal oscillator. Options include:
Divide-by-1–18.75MHz max. crystal
Divide-by-2–37.5MHz max. crystal
Divide-by-4–Standard operation
Divide-by-1024–Low-speed/power
Status register to verify active-interrupt nesting and real-time serial port transmit/receive activity
User-selectable multiplexed or nonmultiplexed external address/data interface
Programmable watchdog timer
Programmable clock-out and reset-out for additional external stand-alone CAN support
Full CAN 2.0B controller (DS80C400 and DS80C410):
15 message centers
Standard 11-bit or extended 29-bit identification modes
Two data byte masks and associated IDs for DeviceNet™, SDS, and other higher-layer CAN protocol
External transmit disable for autobaud
SIESTA low-power mode
100-pin QFP package
ADDENDUM TO SECTION 2: ORDERING INFORMATION
Refer to the individual data sheets for the available versions.
ADDENDUM TO SECTION 3: ARCHITECTURE
The DS80C400 is designed to provide direct compatibility to all of the traditional 80C32 functions, including a 256-byte special func-
tion register (SFR), SRAM memory, a third timer (timer 2), and serial port framing-error detection and automatic address recognition.
Features on the DS80C400 that are compatible with the DS87C520 include a bandgap-based power monitor for interrupt and reset,
timed-access protection, programmable on-board data memory (expanded to 9kB x 8 on the DS80C400, 65kB on the DS80C410/411),
programmable system-clock divide ratios, two serial ports, and a programmable watchdog timer. Expanding on these features, the
DS80C400 also contains an expanded interrupt capability of 16 interrupts with two programmable interrupt priorities, levels for 15 of
the interrupts, and a third-level interrupt priority for power-fail. Additional features include, a math accelerator, a one’s complement
adder, a 1-Wire bus master, a full CAN 2.0B processor (DS80C400/410), an IEEE 802.3-compliant Ethernet media access controller, a
selectable external multiplexed or nonmultiplexed address/data interface, 16-bit, 24-bit paged or 24-bit contiguous addressing oper-
ation, and internally decoded chip enables.
The DS80C400 is designed to function similarly to the DS80C390 and run with external program and data memory. The DS80C400 has
been designed to operate with an extended 24-bit address map and to support external memories with a minimum of external logic.
The DS80C400 also supports an optional extended stack pointer and a 1kB stack memory.
CPU Core and CPU Registers
The CPU core of the DS80C400 executes the same binary-compatible instruction set as that of the 80C32. The principal difference
between the core of the DS80C400 and the 80C32 is the number of clocks required to execute specific instructions. The DS80C400
uses a divide-by-4 of the crystal oscillator, and the 80C32 functions with a divide-by-12 of the crystal oscillator. A machine cycle in the
DS80C400 defaults to four periods of the crystal oscillator. A machine cycle in the 80C32 is interpreted as 12 cycles of the oscillator.
The four MOVX data memory instructions of the DS80C400 have the additional capability of being stretched (external data memory
bus access only) from the original data memory access (read or write) time. The MOVX instruction ranges from two machine cycles to
12 machine cycles across eight programmable settings. This MOVX stretch control is user-selectable with the MD2, MD1, and MD0
bits in the clock control register. The ability to do an instruction-based decrement of the DPTR registers is also now supported, through
additional control bits in the DPS1 and DPS SFRs.
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