Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 113)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
113
Reset Outputs
The microcontroller has one reset output, the RSTOL pin.
Reset Output Low (
RSTOL)
This external output pin is active low whenever the microcontroller is in a reset state. It can be used to signal to external devices that
an otherwise invisible internal reset is in progress. It is active under the following conditions:
• When the processor has entered reset through the RST pin
• During the crystal warmup period following a power-on reset or exit from stop mode (if RGMD = 0)
• During a watchdog timer reset (RSTOL active for two machine cycles)
• During an oscillator failure (if OFDE = 1)
Reset State
Regardless of the source of the reset, the state of the microcontroller is the same while in reset. When in reset, the oscillator is running,
but no program execution is allowed. When the reset source is external, the user must remove the reset stimulus. Anytime power is
applied to the device, completion of the power-on delay removes the reset state automatically.
Resets do not affect the scratchpad RAM. Thus, any data stored in RAM is preserved. The contents of internal MOVX data memory also
remain unaffected by a reset. However, the minimum data retention voltage for these internal memories is not specified, so RAM data
must be assumed lost whenever the POR bit has been set.
The reset state of SFR bits is described in Section 4. Bits that are marked SPECIAL have conditions that can affect their reset state.
Consult the individual bit descriptions for more information. Note that the stack pointer is also reset. Thus, the stack is effectively lost
during a reset, even though the RAM contents cannot be altered. Interrupts and timers are disabled. The watchdog timeout defaults to
its shortest interval on any reset. I/O ports are taken to a weak high state (FFh). This leaves each port pin configured with the data latch
set to a 1. Ports do not go to the 1 state instantly when a reset is applied but are taken high within two machine cycles of asserting a
reset (unless the reset was applied while the device was in stop mode). If the reset is applied while the device is in stop mode, ports
0 and 2 (and port 7, when MUX = 1) are taken high only after the 65,536 crystal oscillator warmup period has elapsed. When the reset
stimulus is removed, program execution begins at address 000000h.
In-System Disable Mode
The in-system disable (ISD) feature allows the device to be three-stated for in-circuit emulation or board testing. During ISD mode, the
device pins take on the following states:
The following procedure is used to enter ISD mode at power-up:
1. Assert reset by pulling RST high.
2. Pull ALE low and pull PSEN high.
3. Verify that at least one of the following pins is high: P2.7, P2.6, and P2.5.
4. Release RST.
5. Device is now in ISD mode; release ALE and PSEN, if desired.
Note: Pins P2.7, P2.6, and P2.5 should not be driven low when RST is released. This places the device into a reserved test mode.
Because these pins have a weak pullup during reset, they can be left floating. The test mode is only sampled on the falling edge of
RST and, once RST is released, its state does not affect device operation. In a similar manner, the ALE, PSEN and RST pins can be
released, once their state does not affect device operation, and ISD mode is invoked. Power must be cycled to exit ISD mode.
DEVICE PIN STATE DURING ISD
XTAL1, XTAL2 Oscillator remains active
RSTOL Driven per I OH3 specification
All other pins True tri-state
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