Slave address mask enable register 1 (saden1), Can 0 message center 11 control register (c0m11c), Can 0 message center 12 control register (c0m12c) – Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement User Manual
Page 66: Can 0 message center 13 control register (c0m13c)
High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
66
Slave Address Mask Enable Register 1 (SADEN1)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
CAN 0 Message Center 11 Control Register (C0M11C)
R = Unrestricted read, C = Clear only, * = See description, -n = Value after reset
This SFR is not present on the DS80C411.
7
6
5
4
3
2
1
0
SFR BAh
SADEN1.7
SADEN1.6
SADEN1.5
SADEN1.4
SADEN1.3
SADEN1.2
SADEN1.1
SADEN1.0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
7
6
5
4
3
2
1
0
SFR BBh
MSRDY
ETI
ERI
INTRQ
EXTRQ
MTRQ
ROW/TIH
DTUP
RW-0
RW-0
RW-0
RW-0
RC-0
R*-0
R*-0
R*-0
CAN 0 Message Center 12 Control Register (C0M12C)
R = Unrestricted read, C = Clear only, * = See description, -n = Value after reset
This SFR is not present on the DS80C411.
SADEN1.7–0
Bits 7–0
Slave address mask enable register 1. This register is a mask enable when comparing serial port 1
addresses for automatic address recognition. When a bit is set in this register, the corresponding
bit location in the SADDR1 register is exactly compared with the incoming serial port 1 data to deter-
mine if a receive interrupt should be generated. When a bit in this register is cleared, the correspond-
ing bit in the SADDR1 register becomes a “don’t care” and is not compared against the incoming data.
All incoming data generates a receive interrupt when this register is cleared.
C0M11C
Bits 7–0
Operation of the bits in this register are identical to those found in the CAN 0 message 1 control regis-
ter (C0M1C: ABh). Please consult the description of that register for more information.
C0M12C
Bits 7–0
Operation of the bits in this register are identical to those found in the CAN 0 message 1 control regis-
ter (C0M1C: ABh). Please consult the description of that register for more information.
C0M13C
Bits 7–0
Operation of the bits in this register are identical to those found in the CAN 0 message 1 control regis-
ter (C0M1C: ABh). Please consult the description of that register for more information.
7
6
5
4
3
2
1
0
SFR BCh
MSRDY
ETI
ERI
INTRQ
EXTRQ
MTRQ
ROW/TIH
DTUP
RW-0
RW-0
RW-0
RW-0
RC-0
R*-0
R*-0
R*-0
CAN 0 Message Center 13 Control Register (C0M13C)
R = Unrestricted read, C = Clear only, * = See description, -n = Value after reset
This SFR is not present on the DS80C411.
7
6
5
4
3
2
1
0
SFR BDh
MSRDY
ETI
ERI
INTRQ
EXTRQ
MTRQ
ROW/TIH
DTUP
RW-0
RW-0
RW-0
RW-0
RC-0
R*-0
R*-0
R*-0
Maxim Integrated