Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 53)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
53
General Issues:
The INTIN vector value does not change when a new interrupt source becomes active and the previous
one has not yet been acknowledged and removed (i.e., microcontroller read of CAN 0 status register or
microcontroller clear of the appropriate INTRQ bit in the respective CAN 0 message control register),
regardless of the fact that the new interrupt has a higher priority or not.
If two properly enabled interrupt sources become active at the same time, the interrupt of highest prior-
ity is indicated. For example, if a message center completes a successful transmission or reception and
both STIE and ERI, ETI are set, the interrupt indicated by the INTIN7–0 vector is that of the status-change
interrupt (i.e., INTIN07 = 01 hex and not the message center interrupt; i.e., INTIN7–0 = MCV).
RXS and TXS are always activated when a transmission or reception is successfully completed. These
bits are reset by the microcontroller writing a 0 to them. Reading the CAN 0 status register removes only
the INTIN7–0 = 01 hex vector, but does not clear these bits. These bits (RXS and TXS) can be set by
either the CAN processor or microcontroller, but are never reset by the CAN controller.
The CAN 0 interrupt is active when an active-interrupt source is indicated in the interrupt vector INTIN7–0.
Changes in the INTIN7–0 value from a previous 00 hex state indicate the interrupt source first detected
by the CAN processor following the nonactive-interrupt state. The INTIN7–0 interrupt values displayed in
C0IR remain in place until the respective interrupt source is removed, independent of other higher- or
lower-priority interrupts that become active prior to clearing the currently displayed interrupt source. The
CAN 0 interrupt to the microcontroller is not active when INTIN7–0 = 00 hex. In all the other cases, the
interrupt line is asserted and the INTIN7–0 vector must be read to determine the current interrupt source.
When the current (INTIN7–0) interrupt source is cleared, INTIN7–0 is changed to reflect the next active
interrupt with the highest priority. The status-change interrupt is asserted if there has been a change in
the CAN 0 status register (if enabled by the appropriate ERIE and/or STIE bit) and the CAN status inter-
rupt state is set. A message center interrupt is indicated if the INTRQ bit in the respective CAN mes-
sage control register is set.
The priority of the next interrupt displayed is fixed. As an example, consider the case in which the cur-
rent INTIN7–0 value is that of a message center interrupt. The current INTIN7–0 interrupt source is
cleared (INTRQ = 0), and the status-change interrupt and another message center interrupt are both
active. The next interrupt indicated by INTIN7–0 should be the status-change interrupt, which has a
higher priority than that of the message center interrupt.
When the current INTIN7–0 interrupt indicated is a status interrupt, and the status register is read, the
INTIN7–0 vector is changed to the next lowest INTIN7–0 value (which is the next highest priority) of the
corresponding message center whose INTRQ bit is set to 1. During this time, the interrupt line to the
microcontroller remains active. The microcontroller either does an RETI and then is forced back into the
same interrupt routine by the active-interrupt line or remains in the interrupt routine until the microcon-
troller has cleared all active-interrupt sources (INTIN7–0 = 00 hex).
An active message center interrupt is cleared by writing a 0 to the INTRQ bit in the respective CAN mes-
sage control register. The interrupt line to the microcontroller goes to an inactive state, and the INTIN7–0
vector is reset to 00 hex, if no other interrupts are active and enabled.
Example case:
t<i>: moment in time
STIE = 1, ERI = 1, ETI = 1
t1: INTRQ[1] = 1, RXS = 1 INTIN = 1, interrupt line = active
t2: INTRQ[15] = 1, TXS = 1 INTIN = 1, interrupt line = active
t3: ERR[2:0] = 3’b101 INTIN = 1, interrupt line = active
t4: Begin processing interrupts by micro INTIN = 1, interrupt line = active
t5: TXS = 1 ≥ 0 INTIN = 1, interrupt line = active
t6: RXS = 1 ≥ 0 INTIN = 1, interrupt line = active
t7: ERR[2:0] = 101 ≥ 111 INTIN = 2, interrupt line = active
t8: INTRQ[15] = 1 ≥ 0 INTIN = 3, interrupt line = active
t9: INTRQ[1] = 1 ≥ 0 INTIN = 0, interrupt line = inactive
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