Can 0 standard global mask register 0 (c0sgm0), Can 0 standard global mask register 1 (c0sgm1), Can 0 extended global mask register 0 (c0egm0) – Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement User Manual
Page 142: Can 0 extended global mask register 1 (c0egm1), Can 0 extended global mask register 2 (c0egm2)
High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
142
CAN 0 Standard Global Mask Register 0 (C0SGM0)
MOVX Address
1
7
6
5
4
3
2
1
0
xxxx06h
MASK28
MASK27
MASK26
MASK25
MASK24
MASK23
MASK22
MASK21
CAN 0 Standard Global Mask Register 1 (C0SGM1)
MOVX Address
1
7
6
5
4
3
2
1
0
xxxx07h
MASK20
MASK19
MASK18
0
0
0
0
0
CAN 0 Extended Global Mask Register 0 (C0EGM0)
CAN standard global mask registers 1–0. These registers function as the mask when performing the
11-bit global identification test on incoming messages for message centers 1–14. If message identifi-
cation masking is disabled (MEME = 0), the incoming message ID field must match the corresponding
message center arbitration value exactly, effectively ignoring the contents of these registers. These reg-
isters are used only when performing the message identification test for message centers configured as
standard receivers (EX = 0) having message ID masking enabled (MEME = 1). Thus, the contents are
ignored by message centers configured to receive messages with extended identifiers (EX = 1). These
registers can be modified only during a software initialization (SWINT = 1).
When MEME = 1, any mask bit in the C0SGM1, C0SGM0 mask programmed to a 0 creates a “don’t care”
condition when the respective bit in the incoming message ID field is compared with the corresponding
arbitration bits in message centers 1–14. Any bit in these masks programmed to a 1 forces the respec-
tive bit in the incoming message ID field to match identically with the corresponding arbitration bits in
message centers 1–14 before said message is loaded into message centers 1–14.
The 5 least significant bits in the C0SGM1 register are not used and do not perform any comparison of
these bit locations. A read of the bits will return 0, while writes are ignored.
MOVX Address
1
7
6
5
4
3
2
1
0
xxxx08h
MASK28
MASK27
MASK26
MASK25
MASK24
MASK23
MASK22
MASK21
CAN 0 Extended Global Mask Register 1 (C0EGM1)
MOVX Address
1
7
6
5
4
3
2
1
0
xxxx09h
MASK20
MASK19
MASK18
MASK17
MASK16
MASK15
MASK14
MASK13
CAN 0 Extended Global Mask Register 2 (C0EGM2)
MOVX Address
1
7
6
5
4
3
2
1
0
xxxx0Ah
MASK12
MASK11
MASK10
MASK9
MASK8
MASK7
MASK6
MASK5
Maxim Integrated