Rockwell Automation 1771-PD PID MODULE (+DU) - Manual (Page 194)

Application Example 2, Periodic Block
Transfer
Appendix C
CĆ10
rung 7* When all of the first five bits of the status monitor byte are
low signifying no errors, annunciator lamp 012/05 turns
off.
rung 8* This rung latches storage bit 050/01 which is used to
precondition the read and write block transfer rungs 13 and
31. It can be latched on three separate conditions:
1st Parallel Branch - When 050/04 is energized (refer to
the explanation for rungs 3 thru 5, load/enter sequence).
2nd Parallel Branch - When bit 050/00 is low (refer to the
explanation for rung 32, power-up load/enter sequence).
3rd Parallel Branch - When bit 012/05 is high (refer to the
explanation for rungs 6 and 7, alarm load/enter sequence).
Anytime bit 050/01 is latched, a load/enter sequence is
initiated. It is subsequently unlatched upon completion of
the sequence (rungs 18 thru 20).
rungs 9
thru 11*
Timer 044
8
is a free-running timer which, when timed out,
latches storage bit 050/07. This bit is subsequently used in
rung 13 as a precondition to the read block transfer
instruction. This allows a read block transfer to occur at a
time interval determined by the preset value of timer 0448.
(This preset value is user-selectable).
Storage bit 050/07 is unlatched by the read block transfer
done bit. Note that in rung 9, timer 044
8
is reset during a
load/enter sequence because storage bit 050/01 is high.
rung 12* Zeros are loaded into timer/counter address 0328. The
boundary tells the PC processor not to look beyond word
0328 for data addresses associated with block transfer
instructions.