GE Industrial Solutions Entellisys System User Manual - Manual (Page 167)

FlexLogic redundancy 167
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11.14 FlexLogic redundancy
11.14.1 Overview
CPU control redundancy scheme utilizes primary/hot backup redundancy approach. CPU A is
the primary and CPU B is the backup. By default, the primary runs as the active CPU and the
backup runs as the inactive CPU. The active CPU has contact outputs and circuit breaker control
commands actuated, and the inactive CPU has contact outputs and circuit breaker control
commands blocked. Only one CPU can be active at any given time. Modbus register “Flex Logic
Active”, address 0x0034, holds 1 when the CPU is active and holds 0 when the CPU is inactive.
11.14.2 Throw-over and throwback
The primary throws over to the backup when one of the following conditions occurs:
1. Primary physical discrete I/O card count is different than the configured discrete I/O card
count (observed from Factory Configuration, CPU Settings screen).
2. During CPU startup, at least one installed node is not commissioned in primary or
communicating with primary.
3. During system steady state, primary loses commission or communication with at least one
node and backup is commissioned and communicating with its entire installed nodes.
4. During system steady state, primary loses commission or communication with its entire
installed nodes.
5. Primary is down.
The backup throws back to the primary when all of the following conditions are met:
1. Primary is running.
2. Primary physical discrete I/O card count matches with the configured discrete I/O card
count.
3. All installed nodes are commissioned in primary and communicating with primary.
Transition time for the throw-over and throwback is within 100 to 200 milliseconds. During the
transition time, all contact outputs and circuit breaker control commands are blocked in both
CPUs.
Throw-over and throwback events are shown below:
• CPUA Assumes Control Logic
• CPUB Assumes Control Logic
• CPUA Relinquishes Control Logic
• CPUB Relinquishes Control Logic