Altera RapidIO MegaCore Function - Manual (Page 103)

Chapter 4: Functional Description 4–57
Logical Layer Modules
August 2014 Altera Corporation RapidIO MegaCore Function
User Guide
■ User implementation of a RapidIO function not supported by this IP core (for
example, data message passing)
■ User implementation of a custom function not specified by the RapidIO protocol,
but which may be useful for the system application
Pass-Through Interface Examples
This section contains two examples, one receiving and the other transmitting a packet
through the Avalon-ST pass-through interface. The RapidIO IP core variation in the
receiving example uses 8-bit device ID, and the variation in the transmitting example
uses 16-bit device ID.
Packet Routed Through Rx Port on Avalon-ST Pass-Through Interface
The following example of a packet routed to the receiver Avalon-ST pass-through
interface is for a variation that only has the Maintenance module and the Avalon-ST
pass-through interface enabled. A packet received on the RapidIO interface with an
ftype
that does not indicate a MAINTENANCE transaction is routed to the receiver port of
the Avalon-ST pass-through interface. The transaction diagram in Figure 4–30 shows
a packet received on this interface.
Figure 4–30. Packet Received on the Avalon-ST Pass-Through Interface (1)
Note to Figure 4–30 :
(1) To improve readability of the figure, the data bus has been split in two and is displayed on two lines.
gen_rx_ready
gen_rx_ valid
gen_rx_startofpacket
gen_rx_endofpacket
gen_rx_data[63:32]
gen_rx_data[31:0]
gen_rx_size[5:0]
gen_rx_empty[2:0]
gen_rx_error
0005AACC CAC80001 06070809 0E0F1011 D37C0000
0C005A5A 02030405 0A0B0C0D 12131415 XXXXXXXX
05
4
0 1 2 3 4 5 6
sysclk