Altera RapidIO MegaCore Function - Manual (Page 28)

2–6 Chapter 2: Getting Started
Integrating Your IP Core in Your Design
RapidIO MegaCore Function August 2014 Altera Corporation
User Guide
For Arria V, Cyclone V, and Stratix V designs, you must add a dynamic
reconfiguration block (Transceiver Reconfiguration Controller) to your design, and
connect it to the RapidIO IP core dynamic reconfiguration signals reconfig_fromgxb
and reconfig_togxb. This block supports offset cancellation. The design compiles
without the Transceiver Reconfiguration Controller, but it cannot function correctly in
hardware.
For information about the number of reconfiguration interfaces you must configure in
your Arria V, Cyclone V, or Stratix V dynamic reconfiguration block, refer to the
descriptions of the reconfig_togxb and reconfig_fromgxb signals in
Table 5–8 on
page 5–4 . An informational message in the RapidIO parameter editor tells you the
required number of reconfiguration interfaces.
f For information about the Altera Transceiver Reconfiguration Controller, refer to the
Altera Transceiver PHY IP Core User Guide .
Transceiver Settings
If you want to modify the high-speed transceiver settings in an Arria II GX, Arria II
GZ, Cyclone IV GX, or Stratix IV GX variation, you must first generate the IP core and
then edit the existing ALTGX megafunction in the Quartus II software. Regenerating
overwrites the changes.
The ALTGX megafunction that is generated in your RapidIO IP core is not accesible
through Qsys. You must edit this megafunction using the Quartus II software.
If your RapidIO IP core targets an Arria V, Cyclone V, or Stratix V device, Altera
recommends you do not modify the default transceiver settings configured in the
Custom PHY IP core instance generated with the RapidIO IP core.
If your RapidIO IP core targets an Arria 10 device, Altera recommends you do not
modify the default transceiver settings configured in the Arria 10 Native PHY IP core.
Adding Transceiver Analog Settings for Arria II GX, Arria II GZ, and Stratix
IV GX Variations
For Arria II GX, Arria II GZ, and Stratix IV GX designs, after you generate the system,
you must create assignments for the high-speed transceiver VCCH settings by
following these instructions:
1. In the Quartus II window, on the Assignments menu, click Assignment Editor.
2. In the <<new>> cell in the To column, type the top-level signal name for your
RapidIO IP core instance td signal.
3. Double-click in the Assignment Name column and click I/O Standard.
4. Double-click in the Value column and click your standard (for example, 1.5-V
PCML) .
5. In the new <<new>> row, repeat steps 2 to 4 for your RapidIO IP core instance rd
signal.