Altera RapidIO MegaCore Function - Manual (Page 181)

Chapter 8: Qsys Design Example 8–7
Running Qsys
August 2014 Altera Corporation RapidIO MegaCore Function
User Guide
■ Master I/O BFM
■ On-Chip Memory
The BFM components are functional only for simulation; you cannot compile this
design example system and program it on a device.
Adding the Master Maintenance BFM
To add the Master Maintenance BFM to your system, perform the following steps:
1. In the IP Catalog, in the search box, type Altera Avalon MM Master BFM.
2. Highlight Altera Avalon MM Master BFM and click Add. The Avalon-MM
Master BFM component is added to the system, and the Avalon-MM Master BFM
parameter editor appears.
3. Under Port Widths and Parameters, leave the default values.
4. Under Port Enables, turn on and turn off options to enable only the following
options:
■ Use the read signal
■ Use the write signal
■ Use the address signal
■ Use the readdata signal
■ Use the readdatavalid signal
■ Use the writedata signal
■ Use the waitrequest signal
5. Click Finish to add the Avalon MM Master BFM to your Qsys system.
6. Right-click on the default name of the new component, mm_master_bfm_0, and
click Rename.
7. Type the new name, master_bfm. The design example requires this name to run.
Adding the Master I/O BFM
To add the Master I/O BFM to your system, perform the following steps:
1. In the Component Library, in the search box, type Altera Avalon MM Master BFM.
2. Highlight Altera Avalon MM Master BFM and click Add. The Avalon-MM
Master BFM component is added to the system, and the Avalon-MM Master BFM
parameter editor appears.
3. Under Port Widths, leave the default values.
4. Under Parameters, set the options in Table 8–5 .
Table 8–5. Set Parameter Options
Option Value
Number of Symbols 8
Burstcount width 6