Altera RapidIO MegaCore Function - Manual (Page 113)

Chapter 4: Functional Description 4–67
Error Detection and Management
August 2014 Altera Corporation RapidIO MegaCore Function
User Guide
■ Illegal Transaction Decode is declared when a request packet for a supported
transaction is too short or if it contains illegal values in some of its fields such as in
these examples:
■ Request packet with priority = 3.
■ NWRITE or NWRITE_R request packets without payload.
■ NWRITE or NWRITE_R request packets with reserved wrsize and wdptr
combination.
■ NWRITE , NWRITE_R, SWRITE, or NREAD request packets for which the address does
not match any enabled address mapping window.
■ NREAD request packet with payload.
■ NREAD request with rdsize that is not an integral number of transfers on all byte
lanes. (The Avalon-MM interface specification requires that all byte lanes be
enabled for read transfers. Therefore, Read Avalon-MM master modules do not
have a byteenable signal).
■ Payload size does not match the size indicated by the rdsize or wrsize and
wdptr
fields.
Response Packets with ERROR Status
An ERROR response packet is sent for NREAD and NWRITE_R and Type 5 ATOMIC request
packets that cause an Illegal Transaction Decode error to be declared. An ERROR
response packet is also sent for NREAD requests if the io_m_rd_readerror input signal
is asserted through the final cycle of the Avalon-MM read transfer.
Avalon-ST Pass-Through Interface
Packets with valid CRCs that are not recognized as being targeted to one of the
implemented Logical layer modules are passed to the Avalon-ST pass-through
interface for processing by user logic.
The RapidIO IP core also provides hooks for user logic to report any error detected by
a user-implemented Logical layer module attached to the Avalon-ST pass-through
interface.
The transmit side of the Avalon-ST pass-through interface provides the gen_tx_error
input signal that behaves essentially the same way as the atxerr input signal
described in
“Physical Layer Receive Buffer” on page 4–14 .
If Enable Avalon-ST pass-through interface is enabled and at least one of the Data
Messages
options Source Operation and Destination Operation is turned on in the
RapidIO parameter editor, the message passing error management input ports in
Table 5–21 are added to the IP core to enable integrated error management.