Altera RapidIO MegaCore Function - Manual (Page 182)

8–8 Chapter 8: Qsys Design Example
Running Qsys
RapidIO MegaCore Function August 2014 Altera Corporation
User Guide
5. Under Port Enables, turn on and turn off options to enable only the following
options:
■ Use the read signal
■ Use the write signal
■ Use the address signal
■ Use the byteenable signal
■ Use the burstcount signal
■ Use the readdata signal
■ Use the readdatavalid signal
■ Use the writedata signal
■ Use the waitrequest signal
6. Click Finish to add the second Avalon MM Master BFM to your Qsys system.
7. Right-click on the default name of the new component, mm_master_bfm_0, and
click Rename.
8. Type the new name, master_bfm_io. The design example requires this name to
run.
Adding the On-Chip Memory
To add on-chip memory to your system, perform the following steps:
1. In the Component Library, in the search box, type On Chip Memory.
2. Highlight On-Chip Memory (RAM or ROM) and click Add. The On-Chip
Memory component is added to the system, and the On-Chip Memory parameter
editor appears.
3. Select 64 as the Data width.
4. Click Finish to retain default settings for other parameters and add the On-Chip
Memory to your Qsys system.
Connecting Clocks and the System Components
You must now connect any unconnected clocks and other components in your system.
To support external connections, you must export them. Click Click to export in the
Export
column for the rapidio_0.clk and rapidio_0.exported_connections ports. The
clk_0.clk_in and clk_0.clk_in_reset signals are already exported.
For the external RapidIO processing elements to access the internal registers of the
RapidIO variation, your system must meet the following criteria:
■ The Maintenance Master port must be connected to the System Maintenance Slave
port.
■ The System Maintenance Slave port Base address must be assigned to address
0x0 .
The following sections show you how to make these connections and assignments,
and others required for the design example.