Altera RapidIO MegaCore Function - Manual (Page 51)

Chapter 4: Functional Description 4–5
Clocking and Reset Structure
August 2014 Altera Corporation RapidIO MegaCore Function
User Guide
f For more information about the supported frequencies for the reference clock in your
RapidIO variation, refer to the relevant device handbook.
Other Input Clocks
In variations that target a device for which the transceivers are configured with the
ALTGX megafunction, and not with a Transceiver PHY IP core, the transceiver's
calibration-block clock is called cal_blk_clk.
In Arria V, Cyclone V, and Stratix V devices, the transceiver has an additional clock,
phy_mgmt_clk
, which clocks the software interface to the transceiver. In Arria 10
devices, the transceiver has an input clock bus tx_bonding_clocks_chN. These clocks
should be driven by the external TX transceiver PLL. Arria 10 variations also have an
option interface, the Arria 10 Native PHY dynamic reconfiguration interface, which
includes a clock signal for each transceiver channel.
Clock Domains
The Physical layer's buffers implement clock domain crossing between the Avalon
system clock domain and the Physical layer's clock domains.
In systems created with Qsys, the system interconnect manages clock domain crossing
if some of the components of the system run on a different clock. For optimal
throughput, run all the components in the datapath on the same clock.
1
All of the clock inputs for the Logical layer modules must be connected to the same
clock source as the Avalon system clock.