Altera RapidIO MegaCore Function - Manual (Page 32)

2–10 Chapter 2: Getting Started
Instantiating Multiple RapidIO IP Cores
RapidIO MegaCore Function August 2014 Altera Corporation
User Guide
1 Before compiling your design in the Quartus II software, you must apply the
constraints as described in
“Specifying Constraints” on page 2–8 .
Instantiating Multiple RapidIO IP Cores
If you want to instantiate multiple RapidIO IP cores, a few additional steps are
required. The following sections outline these steps.
Clock and Signal Requirements for Arria V, Cyclone V, and Stratix V
Variations
When your design targets an Arria V, Cyclone V, or Stratix V device, the transceivers
are configured with the Altera Custom PHY IP core. When your design contains
multiple RapidIO IP cores, the Quartus II Fitter handles the merge of multiple Custom
PHY IP cores in the same transceiver block automatically. To merge multiple Custom
PHY IP cores in the same transceiver block, the Fitter requires that the
phy_mgmt_clk_reset
input signal for all of the merged IP cores be driven by the same
source.
If you have different RapidIO IP cores in different transceiver blocks on your device,
you may choose to include multiple Transceiver Reconfiguration Controllers in your
design. However, you must ensure that the Transceiver Reconfiguration Controllers
that you add to your design have the correct number of interfaces to control dynamic
reconfiguration of all your RapidIO IP core transceivers. The correct total number of
reconfiguration interfaces is the sum of the reconfiguration interfaces for each
RapidIO IP core; the number of reconfiguration interfaces for each RapidIO IP core is
the number of channels plus one. You must ensure that the reconfig_togxb and
reconfig_fromgxb
signals of an individual RapidIO IP core connect to a single
Transceiver Reconfiguration Controller.
For example, if your design includes one 4× RapidIO IP core and three 1× RapidIO IP
cores, the Transceiver Reconfiguration Controllers in your design must include eleven
dynamic reconfiguration interfaces: five for the 4× RapidIO IP core, and two for each
of the 1× RapidIO IP cores. The dynamic reconfiguration interfaces connected to a
single RapidIO IP core must belong to the same Transceiver Reconfiguration
Controller. In most cases, your design has only a single Transceiver Reconfiguration
Controller, which has eleven dynamic reconfiguration interfaces. If you choose to use
two Transceiver Reconfiguration Controllers, for example, to accommodate
placement and timing constraints for your design, each of the RapidIO IP cores must
connect to a single Transceiver Reconfiguration Controller.
f
For Information About Refer To
Compiling your design
Quartus II Incremental Compilation for Hierarchical and Team-
Based Design
chapter in volume 1 of the Quartus II Handbook
Programming the device
Device Programming section in volume 3 of the Quartus II
Handbook