Altera RapidIO MegaCore Function - Manual (Page 143)

Chapter 6: Software Interface 6–11
Transport and Logical Layer Registers
August 2014 Altera Corporation RapidIO MegaCore Function
User Guide
Transport and Logical Layer Registers
This section lists the Transport and Logical layer registers. Table 6–2 provides a
memory map of all accessible registers. This address space is accessible to the user
through the System Maintenance Avalon-MM slave interface.
Capability Registers (CARs)
Table 6–12 through Table 6–19 describe the capability registers.
IN_PENA [21] RW
Input port receive enable:
'b0—Port is stopped and only enabled to respond I/O
Logical MAINTENANCE requests. Other requests return
packet-not-accepted
control symbols to force an error
condition to be signaled by the sending device
'b1—Port is enabled to respond to any packet
1'b1
ERR_CHK_DIS [20] RW
This bit controls all RapidIO transmission error checking:
'b0—Error checking and recovery is enabled
'b1—Error checking and recovery is disabled
Device behavior when error checking and recovery is
disabled and an error condition occurs is undefined.
1'b0
Multicast-event
Participant
[19] RW
Send incoming Multicast-event control symbols to this port
(multiple port devices only).
1'b0
RSRV [18] RO Reserved 1'b0
Enumeration
Boundary
[17] RO This feature is not supported. 1'b0
RSRV [16:12] RO Reserved 5'b0
Re-transmit
Suppression Mask
[11:4] RO This feature is not supported. 8’b0
RSRV [3:1] RO Reserved 3’b0
PORT_TYPE [0] RO
This bit indicates the port type, parallel or serial.
'b0—Parallel port
'b1—Serial port
1'b1
Note to Table 6–11 :
(1) Reflects the choice made in the RapidIO parameter editor.
Table 6–11. Port 0 Control CSR—Offset: 0x15C (Part 2 of 2)
Field Bits Access Function Default
Table 6–12. Device Identity CAR—Offset: 0x00
Field Bits Access Function Default
DEVICE_ID [31:16] RO Hard-wired device identifier (1)
VENDOR_ID [15:0] RO Hard-wired device vendor identifier (1)
Note to Table 6–12 :
(1) The default value is set in the RapidIO parameter editor.