Altera RapidIO MegaCore Function - Manual (Page 29)

Chapter 2: Getting Started 2–7
Integrating Your IP Core in Your Design
August 2014 Altera Corporation RapidIO MegaCore Function
User Guide
External Transceiver PLL
RapidIO IP cores that target an Arria 10 device require an external TX transceiver PLL
to compile and to function correctly in hardware. You must instantiate and connect
this IP core to the RapidIO IP core.
You can create an external transceiver PLL from the IP Catalog. Select the ATX PLL IP
core. In the ATX TX PLL parameter editor, set the following parameter values:
■ Set PLL output frequency to one half the value you select for the Baud rate
parameter in the RapidIO parameter editor. The transceiver performs dual edge
clocking, using both the rising and falling edges of the input clock from the PLL.
Therefore, this PLL output frequency setting supports the customer-selected
maximum data rate on the RapidIO link.
■ Set PLL reference clock frequency to the value you select for the Reference clock
frequency
parameter in the RapidIO parameter editor.
■ Turn on Include Master Clock Generation Block.
■ Turn on Enable bonding clock output ports.
■ Set PMA interface width to 20.
When you generate a RapidIO IP core, the Quartus II software also generates the HDL
code for an ATX PLL, in the file
<variation>/altera_rapidio_140/synth/altera_rapidio_tx_pll.sv. However, the HDL
code for the RapidIO IP core does not instantiate the ATX PLL. If you choose to use
the ATX PLL provided with the RapidIO IP core, you must instantiate and connect the
ATX PLL instance with the RapidIO IP core in user logic.
You must connect the TX PLL IP core to the RapidIO IP core according to the
following rules.
For an example of how to configure and connect a TX PLL IP core to the other system
components, such as the external reset controller, refer to the cleartext testbench files
and
Chapter 7, Testbenches .
f For information about the connection requirements and flexibility, refer to the Arria 10
Transceiver PHY User Guide .
Table 2–1. External Transceiver TX PLL Connections to RapidIO IP Core
Signal Direction Connection Requirements
pll_refclk0 Input
Drive the PLL pll_refclk0 input port and the RapidIO IP
core reference clock clk signal from the same clock
source. The minimum allowed frequency for the
pll_refclk0
clock in an Arria 10 ATX PLL is 100 MHz.
tx_bonding_clocks
[(6 x <number of
lanes>)–1:0]
Output
Connect tx_bonding_clocks[6n+5:6n] to the
tx_bonding_clocks_chN
input bus of transceiver
channel N, for each transceiver channel N that connects to
the RapidIO link. The transceiver channel input ports are
RapidIO IP core input ports.