Altera RapidIO MegaCore Function - Manual (Page 54)

4–8 Chapter 4: Functional Description
Clocking and Reset Structure
RapidIO MegaCore Function August 2014 Altera Corporation
User Guide
In systems generated by Qsys, this circuit is generated automatically. However, if
your RapidIO IP core variation is not generated by Qsys, you must implement logic to
ensure the minimal hold time and synchronous deassertion of the reset_n input
signal to the RapidIO IP core.
Reset Controller
All non-Arria 10 RapidIO IP core variations include a dedicated reset control module
to handle the specific requirements of the internal transceiver module. Arria 10
RapidIO IP core variations do not include a reset controller.
The reset control module is named riophy_reset. This riophy_reset module is
defined in the riophy_reset.v clear-text Verilog HDL source file, and is instantiated
inside the top-level module found in the clear text <variation name>_riophy_xcvr.v
Verilog HDL source file.
The riophy_reset module controls all of the RapidIO IP core's internal reset signals.
In particular, it generates the recommended reset sequence for the transceiver. The
reset sequence and requirements vary among device families. For details, refer to the
relevant device handbook.
Reset Requirements for Arria V, Cyclone V, and Stratix V Variations
Arria V, Cyclone V, and Stratix V variations have the following additional constraints:
■ The Custom PHY IP core phy_mgmt_clk_reset signal and the RapidIO IP core
reset_n
signal must be driven from the same source, with the caveat that the
phy_mgmt_clk_reset signal is active high and the reset_n signal is active low. The
two reset signals must be asserted synchronously, but deasserted each according
to its corresponding clock.
Figure 4–4 on page 4–9 shows a circuit that ensures the
requirements for these two reset signals are met.
■ You must ensure that the system does not deassert reset_n and
phy_mgmt_clk_reset
when the Altera Transceiver Reconfiguration Controller
reconfig_busy signal is asserted. The RapidIO IP core must remain in reset until
the Transceiver Reconfiguration Controller is available.
The assertion of reset_n causes the whole IP core to reset. In Arria V, Cyclone V, and
Stratix V devices, the requirement that phy_mgmt_clk_reset be asserted with reset_n
ensures that the PHY IP core resets with the RapidIO IP core. While the module is
held in reset, the Avalon-MM waitrequest outputs are driven high and all other
outputs are driven low. When the module comes out of the reset state, all buffers are
empty. Refer to
Chapter 6, Software Interface for the default value of registers after
reset.