Altera RapidIO MegaCore Function - Manual (Page 49)

Chapter 4: Functional Description 4–3
Clocking and Reset Structure
August 2014 Altera Corporation RapidIO MegaCore Function
User Guide
Clocking and Reset Structure
RapidIO IP Core Clocking
The RapidIO IP core has the following clock inputs:
■ sysclk: Avalon system clock.
■ clk: reference clock for the transceiver Tx PLL and Rx PLL. In Arria 10 variations,
this clock port drives only the Rx PLL.
■ cal_blk_clk: t ransceiver calibration-block clock (Arria II GX, Arria II GZ,
Cyclone IV GX, and Stratix IV GX variations only).
■ reconfig_clk: t ransceiver reconfiguration interface clock (Arria II GX, Arria II
GZ, Cyclone IV GX, and Stratix IV GX variations only).
■ phy_mgmt_clk: t ransceiver software interface clock (Arria V, Arria V GZ, Cyclone
V, and Stratix V variations only).
■ tx_bonding_clocks_chN: Arria 10 device transceiver channel clocks for the
transceiver channel that corresponds to RapidIO lane N (Arria 10 variations only)
In addition, if you turn on Enable transceiver dynamic reconfiguration for your
RapidIO Arria 10 variation, the IP core includes a reconfig_clk_chN input clock
for each RapidIO lane N. Each reconfig_clk_chN clocks the
Arria 10 Native
PHY dynamic reconfiguration interface for RapidIO lane N.
The RapidIO IP core provides the following clock outputs from the transceiver:
■ Transceiver receiver clock (recovered clock) (rxgxbclk)
■ Recovered data clock (rxclk). Recovered clock that drives the receiver modules in
the Physical layer.
■ Transceiver transmit-side clock (txclk). Main clock for the transmitter modules in
the Physical layer.
RapidIO IP core 2x and 4x variations are implemented in the transceiver TX bonded
mode. All channels of a 2x or 4x variation, on any supported device, must reside in a
single transceiver block.
To support this requirement in Arria II GX, Arria II GZ, Cyclone IV GX, and Stratix IV
GX variations, the starting channel number for a 4x variation must be a multiple of
four.
When you generate a custom non-Arria 10 IP core, the
<
variation name>_constraints.tcl script contains the required assignments. When you
run the script, the constraints are applied to your project.
Avalon System Clock
The Avalon system clock drives the Transport and Logical layer modules; its
frequency is nominally the same frequency as the Physical layer's internal clocks
txclk
and rxclk, but it can differ by up to ±50% provided the Avalon system clock
meets f
MAX
limitations. This clock is called sysclk. Qsys allows you to export the
clock signal with a name of your choice.