Altera RapidIO MegaCore Function - Manual (Page 186)

8–12 Chapter 8: Qsys Design Example
Simulating the System
RapidIO MegaCore Function August 2014 Altera Corporation
User Guide
1 If you are prompted to save your changes to rio_sys.qsys, click Save.
Generating the system files, the simulation models, and the environment takes a
few minutes.
When the Qsys system is generated successfully, the system HDL files are added
to your project directory and are ready to be simulated with the Quartus II
software.
8. After generation completes successfully, click Exit to close Qsys.
1 Although this design example requires the Verilog HDL target output, you can
alternatively select VHDL for a project of your own.
Simulating the System
To simulate your system with the sample Verilog HDL testbench, follow these steps:
1. Copy the following files from the \ip\altera\rapidio\lib\rio\qsys_cust_demo
subdirectory of your Quartus II installation directory to your Quartus II project
directory:
■ rio_sys_tb.v
■ sim.do
■ test_bench.v
■ test_input.v
■ test_result.v
2. Start the ModelSim software. On the File menu, change directory to your
Quartus II project directory.
3. Type the following command at the ModelSim command prompt:
do sim.do
r
The RapidIO design example performs the following transactions in simulation:
■ Sends a sequence of read requests to the internal registers of the IP core
■ Sets up other internal registers of the IP core for MAINTENANCE and I/O transactions
and reads the registers to ensure the write operations completed
■ Writes data to the Maintenance slave, reads it back, and verifies data integrity
■ Sends burst transfer write and read requests to the IP core to send out on the
RapidIO link, and verifies data integrity
When simulation completes, on the File menu, click Quit to close the ModelSim
software.