Altera RapidIO MegaCore Function - Manual (Page 159)

Chapter 6: Software Interface 6–27
Transport and Logical Layer Registers
August 2014 Altera Corporation RapidIO MegaCore Function
User Guide
0x00 Rx Doorbell
External Avalon-MM master that generates or receives
doorbell messages.
0x04 Rx Doorbell Status
0x08 Tx Doorbell Control
0x0C Tx Doorbell
0x10 Tx Doorbell Status
0x14 Tx Doorbell Completion
0x18
Tx Doorbell Completion
Status
0x1C Tx Doorbell Status Control
0x20 Doorbell Interrupt Enable
0x24 Doorbell Interrupt Status
Table 6–57. Doorbell Message Module Memory Map (Part 2 of 2)
Address Name Used by
Table 6–58. Rx Doorbell—Offset: 0x00
Field Bits Access Function Default
LARGE_SOURCE_ID
(MSB)
[31:24] RO
Reserved if the system does not support 16-bit device ID.
8'b0 MSB of the DOORBELL message initiator device ID if the system
supports 16-bit device ID.
SOURCE_ID [23:16] RO Device ID of the DOORBELL message initiator 8'b0
INFORMATION (MSB) [15:8] RO Received DOORBELL message information field, MSB 8'b0
INFORMATION (LSB) [7:0] RO Received DOORBELL message information field, LSB 8'b0
Table 6–59. Rx Doorbell Status—Offset: 0x04
Field Bits Access Function Default
RSRV [31:8] RO Reserved 24’b0
FIFO_LEVEL [7:0] RO
Shows the number of available DOORBELL messages in the Rx FIFO.
A maximum of 16 received messages is supported.
8'h0
Table 6–60. Tx Doorbell Control—Offset: 0x08
Field Bits Access Function Default
RSRV [31:2] RO Reserved 30'h0
PRIORITY [1:0] RW
Request Packet’s priority. 2’b11 is not a valid value for the
priority
field. An attempt to write 2’b11 to this field will be
overwritten as 2’b10.
2'h0
Table 6–61. Tx Doorbell—Offset: 0x0C (Part 1 of 2)
Field Bits Access Function Default
LARGE_DESTINATION_ID
(MSB)
[31:24]
RO Reserved if the system does not support 16-bit device ID.
8'h0
RW
MSB of the targeted RapidIO processing element device ID if
the system supports 16-bit device ID.
DESTINATION_ID [23:16] RW Device ID of the targeted RapidIO processing element 8'h0