Altera RapidIO MegaCore Function - Manual (Page 56)

4–10 Chapter 4: Functional Description
Physical Layer
RapidIO MegaCore Function August 2014 Altera Corporation
User Guide
RapidIO IP Core Reset Behavior
Consistent with normal operation, following the IP core reset sequence, the
Initialization state machine transitions to the SILENT state.
f For details of the RapidIO Initialization state machine, refer to section 4.12 of Part 6:
LP-Serial Physical Layer Specification of the RapidIO Interconnect Specification, Revision
2.1, available at
www.rapidio.org .
If two communicating RapidIO IP cores are reset one after the other, one of the IP
cores may enter the Input Error Stopped state because the other IP core is in the SILENT
state while this one is already initialized. The initialized IP core enters the Input Error
Stopped state and subsequently recovers.
Physical Layer
This section describes features and blocks of the 1x, 2x, or 4x serial Physical layer of
the RapidIO IP core.
Figure 4–5 on page 4–11 shows a high-level block diagram of the
RapidIO IP core’s Physical layer.
Features
The Physical layer has the following features:
■ Port initialization
■ Transmitter and receiver with the following features:
■ One, two, or four lane high-speed data serialization and deserialization (up to
5.0 Gbaud for 1x variations with 32-bit Atlantic
interface; up to 5.0 Gbaud for
2x and 4x variations with 64-bit Atlantic interface)
■ Clock and data recovery (receiver)
■ 8B10B encoding and decoding
■ Lane synchronization (receiver)
■ Packet/control symbol assembly and delineation
■ Cyclic redundancy code (CRC) generation and checking on packets
■ Control symbol CRC-5 generation and checking
■ Error detection
■ Pseudo-random idle sequence generation
■ Idle sequence removal
■ Software interface (status/control registers)
■ Flow control (ackID tracking)
■ Time-out on acknowledgements
■ Order of retransmission maintenance and acknowledgements
■ ackID assignment
■ ackID synchronization after reset