Altera RapidIO MegaCore Function - Manual (Page 161)

Chapter 6: Software Interface 6–29
Transport and Logical Layer Registers
August 2014 Altera Corporation RapidIO MegaCore Function
User Guide
Table 6–65. Tx Doorbell Status Control—Offset: 0x1C
Field Bits Access Function Default
RSRV [31:2] RO Reserved 30'h0
ERROR [1] RW
If set, outbound DOORBELL messages that received a response with
ERROR
status, or were timed out, are stored in the Tx Completion
FIFO. Otherwise, no error reporting occurs.
1'h0
COMPLETED [0] RW
If set, responses to successful outbound DOORBELL messages are
stored in the Tx Completion FIFO. Otherwise, these responses are
discarded.18
1'h0
Table 6–66. Doorbell Interrupt Enable—Offset: 0x20
Field Bits Access Function Default
RSRV [31:3] RO Reserved 29'b0
TX_CPL_OVERFLOW [2] RW Tx Doorbell Completion Buffer Overflow Interrupt Enable 1'h0
TX_CPL [1] RW Tx Doorbell Completion Interrupt Enable 1'h0
RX [0] RW Doorbell Received Interrupt Enable 1'h0
Table 6–67. Doorbell Interrupt Status—Offset: 0x24
Field Bits Access Function Default
RSRV [31:3] RO Reserved 29'h0
TX_CPL_OVERFLOW [2] RW1C
Interrupt asserted due to Tx Completion buffer overflow. This bit
remains set until at least one entry is read from the Tx
Completion FIFO. After reading at least one entry, software
should clear this bit. It is not necessary to read all of the Tx
Completion FIFO entries.
1'h0
TX_CPL [1] RW1C Interrupt asserted due to Tx completion status 1'h0
RX [0] RW1C Interrupt asserted due to received messages 1'h0