LSI 53C875A - Manual (Page 11)

Contents xi
6.9 PCI Configuration Register Read 6-13
6.10 PCI Configuration Register Write 6-14
6.11 32-Bit Operating Register/SCRIPTS RAM Read 6-15
6.12 64-Bit Address Operating Register/SCRIPTS RAM Read 6-16
6.13 32-Bit Operating Register/SCRIPTS RAM Write 6-17
6.14 64-Bit Address Operating Register/SCRIPTS RAM Write 6-18
6.15 Nonburst Opcode Fetch, 32-Bit Address and Data 6-20
6.16 Burst Opcode Fetch, 32-Bit Address and Data 6-22
6.17 Back-to-Back Read, 32-Bit Address and Data 6-24
6.18 Back-to-Back Write, 32-Bit Address and Data 6-26
6.19 Burst Read, 32-Bit Address and Data 6-28
6.20 Burst Read, 64-Bit Address and Data 6-30
6.21 Burst Write, 32-Bit Address and Data 6-32
6.22 Burst Write, 64-Bit Address and 32-Bit Data 6-34
6.23 External Memory Read 6-36
6.24 External Memory Write 6-40
6.25 Normal/Fast Memory (
≥
128 Kbytes) Single Byte
Access Read Cycle 6-42
6.26 Normal/Fast Memory (
≥
128 Kbytes) Single Byte
Access Write Cycle 6-43
6.27 Normal/Fast Memory (
≥
128 Kbytes) Multiple Byte
Access Read Cycle 6-44
6.28 Normal/Fast Memory (
≥
128 Kbytes) Multiple Byte
Access Write Cycle 6-46
6.29 Slow Memory (
≤
128 Kbytes) Read Cycle 6-48
6.30 Slow Memory (
≤
128 Kbytes) Write Cycle 6-49
6.31
≤
64 Kbytes ROM Read Cycle 6-50
6.32
≤
64 Kbyte ROM Write Cycle 6-51
6.33 Initiator Asynchronous Send 6-52
6.34 Initiator Asynchronous Receive 6-53
6.35 Target Asynchronous Send 6-54
6.36 Target Asynchronous Receive 6-55
6.37 Initiator and Target Synchronous Transfer 6-57
6.38 LSI53C875A 160-Pin PQFP Mechanical Drawing 6-58
6.39 169-Pin BGA Mechanical Drawing 6-61
B.1 16 Kbyte Interface with 200 ns Memory B-1
B.2 64 Kbyte Interface with 150 ns Memory B-2