LSI 53C875A - Manual (Page 45)

SCSI Functional Description 2-23
Load and Store instructions, refer to Chapter 5, “SCSI SCRIPTS
Instruction Set.”
2.2.9 JTAG Boundary Scan Testing
The LSI53C875A includes support for JTAG boundary scan testing in
accordance with the IEEE 1149.1 specification with one exception, which
is explained in this section. This device accepts all required boundary
scan instructions including the optional CLAMP, HIGH-Z, and IDCODE
instructions.
The LSI53C875A uses an 8-bit instruction register to support all
boundary scan instructions. The data registers included in the device are
the Boundary Data register, the IDCODE register, and the Bypass
register. This device can handle a 10 MHz TCLK frequency for TDO and
TDI.
Due to design constraints, the RST/ pin (system reset) always 3-states
the SCSI pins when it is asserted. Boundary scan logic does not control
this action, and this is not compliant with the specification. There are two
solutions that resolve this issue:
1. Use the RST/ pin as a boundary scan compliance pin. When the pin
is deasserted, the device is boundary scan compliant and when
asserted, the device is noncompliant. To maintain compliance the
RST/ pin must be driven HIGH.
2. When RST/ is asserted during boundary scan testing the expected
output on the SCSI pins must be the HIGH-Z condition, and not what
is contained in the boundary scan data registers for the SCSI pin
output cells.
2.2.10 SCSI Loopback Mode
The LSI53C875A loopback mode allows testing of both initiator and
target functions and, in effect, lets the chip communicate with itself.
When the Loopback Enable bit is set in the
SCSI Test Two (STEST2)
register, bit 4, the LSI53C875A allows control of all SCSI signals whether
the chip is operating in the initiator or target mode. For more information
on this mode of operation refer to the LSI Logic SCSI SCRIPTS
Processor Programming Guide.