LSI 53C875A - Manual (Page 318)

IX-8 Index
reset 3-4
input 6-10
SCSI offset (ROF) 4-89
response ID one (RESPID1) 4-86
response ID zero (RESPID0) 4-86
return instruction 5-27
revision ID (RID) 4-6
ROM
flash and memory interface signals 3-11
pin 2-49
RST/ 3-4
S
SACK 2-42
SACK/ status (ACK) 4-39
SACs 2-19
SATN/ status (ATN) 4-39
SBSY/ status (BSY) 4-39
SC_D/ status (C_D) 4-39
SCLK 3-8
(SCLK) 4-88
quadrupler enable (QEN) 4-88
quadrupler select (QSEL) 4-89
SCNTL0 2-25
SCNTL1 2-24 , 2-25
SCNTL3 2-36
scratch
byte register (SBR) 4-70
register A (SCRATCHA) 4-65
register B (SCRATCHB) 4-99
registers C–R (SCRATCHC–SCRATCHR) 4-99
script fetch selector (SFS) 4-101
SCRIPTS
(SCPTS) 4-82
instruction 2-46
interrupt instruction received (SIR) 4-40 , 4-69
processor 2-17
internal RAM for instruction storage 2-18
performance 2-17
RAM 2-3 , 2-18
running (SRUN) 4-51
SCSI
ATN condition - target mode (M/A) 4-73
bus control lines (SBCL) 4-38
bus data lines (SBDL) 4-98
bus interface 2-32
byte count (SBC) 4-107
C_D/ signal (C_D) 4-45
chip ID (SCID) 4-30
clock 3-8
control enable (SCE) 4-89
control one (SCNTL1) 4-23
control three (SCNTL3) 4-28
control two (SCNTL2) 4-26
control zero (SCNTL0) 4-20
data high impedance (ZSD) 4-59
destination ID (SDID) 4-35
disconnect unexpected (SDU) 4-26
encoded destination ID 5-20
FIFO test read (STR) 4-91
FIFO test write (STW) 4-93
first byte received (SFBR) 4-36
functional description 2-16
GPIO signals 3-10
gross error (SGE) 4-74 , 4-77
I_O/ signal (I/O) 4-45
input data latch (SIDL) 4-93
instructions
block move 5-6
I/O 5-13
read/write 5-22
interface signals 3-8
interrupt enable one (SIEN1) 4-75
interrupt enable zero (SIEN0) 4-73
interrupt pending (SIP) 4-50
interrupt status one (SIST1) 4-78
interrupt status zero (SIST0) 4-76
interrupts 2-42
isolation mode (ISO) 4-88
longitudinal parity (SLPAR) 4-79
loopback mode 2-23
loopback mode (SLB) 4-89
low level mode (LOW) 4-90
MSG/ signal (MSG) 4-45
output control latch (SOCL) 4-37
output data latch (SODL) 4-94
parity control 2-26
parity error (PAR) 4-75
performance 1-5
phase 5-11 , 5-28
phase mismatch - initiator mode 4-73
reset condition (RST) 4-75
RST/ received (RST) 4-78
RST/ signal (RST) 4-43
SCRIPTS operation 5-2
sample instruction 5-3
SDP0/ parity signal (SDP0) 4-43
SDP1 signal (SDP1) 4-47
selected as ID (SSAID) 4-87
selector ID (SSID) 4-38
serial EEPROM access 2-50
signals 3-9
status one (SSTAT1) 4-43
status two (SSTAT2) 4-46
status zero (SSTAT0) 4-42
synchronous offset maximum (SOM) 4-88
synchronous offset zero (SOZ) 4-87
synchronous transfer period (TP[2:0]) 4-31
termination 2-32
test four (STEST4) 4-94
test one (STEST1) 4-88
test three (STEST3) 4-91
test two (STEST2) 4-89
test zero (STEST0) 4-87
timer one (STIME1) 4-85
timer zero (STIME0) 4-83
TolerANT technology 1-4
transfer (SXFER) 4-31
true end of process (TEOP) 4-55
Ultra SCSI 2-20
valid (VAL) 4-38
wide residue (SWIDE) 4-81
SCSI-2
fast transfers
10.0 Mbytes (8-bit transfers)
40 MHz clock 6-56
20.0 Mbytes (16-bit transfers)
40 MHz clock 6-56
SCTRL signals 3-9
SD[15:0] 3-9
second dword 5-13 , 5-21 , 5-23 , 5-32 , 5-34 , 5-37