LSI 53C875A - Manual (Page 285)

PCI and External Memory Interface Timing Diagrams 6-47
Figure 6.28 Normal/Fast Memory (
≥ =
128 Kbytes) Multiple Byte Access Write Cycle
(Cont.)
MAD
(Driven by LSI53C875A;
MAS1/
(Driven by LSI53C875A)
MAS0/
(Driven by LSI53C875A)
MCE/
(Driven by LSI53C875A)
MOE/
(Driven by LSI53C875A)
MWE/
(Driven by LSI53C875A)
15 18 20 22 24 26 28 30
CLK
(Driven by System)
PAR
(Driven by Master-Addr;
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C875A)
STOP/
(Driven by LSI53C875A)
DEVSEL/
(Driven by LSI53C875A)
AD
(Driven by Master-Addr;
C_BE[3:0]/
(Driven by Master)
FRAME/
(Driven by Master)
LSI53C875A-Data)
LSI53C875A-Data)
16 32
Data In
Byte Enable
Data Out
Lower
Address
Data Out
In