LSI 53C875A User Manual
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Functional Description
2.1.2.10 Memory Read Multiple Command
This command is identical to the Memory Read command except that it
additionally indicates that the master may intend to fetch more than one
cache line before disconnecting. The LSI53C875A supports PCI Memory
Read Multiple functionality and issues Memory Read Multiple commands
on the PCI bus when the Read Multiple Mode is enabled. This mode is
enabled by setting bit 2 (ERMP) of the
register. If
cache mode is enabled, a Memory Read Multiple command is issued on
all read cycles, except opcode fetches, when the following conditions are
met:
•
The CLSE bit (Cache Line Size Enable, bit 7,
register) and the ERMP bit (Enable Read Multiple, bit 2,
register) are set.
•
The
register for each function contains a legal burst
size value (2, 4, 8, 16, 32, or 64) and that value is less than or equal
to the DMODE burst size.
•
The transfer will cross a cache line boundary.
When these conditions are met, the chip issues a Memory Read Multiple
command instead of a Memory Read during all PCI read cycles.
Burst Size Selection – The Read Multiple command reads in multiple
cache lines of data in a single bus ownership. The number of cache lines
to read is a multiple of the cache line size specified in Revision 2.2 of
the PCI specification. The logic selects the largest multiple of the cache
line size based on the amount of data to transfer, with the maximum
allowable burst size determined from the
burst size
bits, and the
, bit 2.
2.1.2.11 Dual Address Cycle (DAC) Command
The LSI53C875A performs DACs when 64-bit addressing is required.
Refer to the PCI 2.2 specification. If any of the selector registers contain
a nonzero value, a DAC is generated. See 64-bit SCRIPTS Selectors in
Chapter 4, “Registers,”
for additional information.
2.1.2.12 Memory Read Line Command
This command is identical to the Memory Read command, except that it
additionally indicates that the master intends to fetch a complete cache