16 interrupt handling, Interrupt handling – LSI 53C875A User Manual
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SCSI Functional Description
2-37
•
Ultra SCSI Enable bit,
register bit 7.
Setting this bit enables Ultra SCSI synchronous transfers in systems
that use the internal SCSI clock quadrupler.
•
TolerANT Enable bit,
register bit 7. Active
negation must be enabled for the LSI53C875A to perform Ultra SCSI
transfers.
2.2.16 Interrupt Handling
The SCRIPTS processors in the LSI53C875A perform most functions
independently of the host microprocessor. However, certain interrupt
situations must be handled by the external microprocessor. This section
explains all aspects of interrupts as they apply to the LSI53C875A.
2.2.16.1 Polling and Hardware Interrupts
The external microprocessor is informed of an interrupt condition by
polling or hardware interrupts. Polling means that the microprocessor
must continually loop and read a register until it detects a bit that is set
indicating an interrupt. This method is the fastest, but it wastes CPU time
that could be used for other system tasks. The preferred method of
detecting interrupts in most systems is hardware interrupts. In this case,
the LSI53C875A asserts the Interrupt Request (IRQ/) line that interrupts
the microprocessor, causing the microprocessor to execute an interrupt
service routine. A hybrid approach would use hardware interrupts for
long waits, and use polling for short waits.
2.2.16.2 Registers
The registers in the LSI53C875A that are used for detecting or defining
interrupts are
Interrupt Status Zero (ISTAT0)
,
SCSI Interrupt Status One (SIST1)
,
SCSI Interrupt Enable Zero (SIEN0)
, and
.
ISTAT – The ISTAT register includes the
Interrupt Status Zero (ISTAT0)
,
, and
registers. It is the only register that can be accessed as a
slave during the SCRIPTS operation. Therefore, it is the register that is