LSI 53C875A - Manual (Page 283)

PCI and External Memory Interface Timing Diagrams 6-45
Figure 6.27 Normal/Fast Memory (
≥ =
128 Kbytes) Multiple Byte Access Read Cycle
(Cont.)
MAD
(Addr Driven by LSI53C875A ;
MAS1/
(Driven by LSI53C875A)
MAS0/
(Driven by LSI53C875A)
MCE/
(Driven by LSI53C875A)
MOE/
(Driven by LSI53C875A)
MWE/
(Driven by LSI53C875A)
15 18 20 22 24 26 28 30
Data driven by Memory)
CLK
(Driven by System)
PAR
(Driven by LSI53C875A-
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C875A)
STOP/
(Driven by LSI53C875A)
DEVSEL/
(Driven by LSI53C875A)
AD
(Driven by LSI53C875A-
C_BE[3:0]/
(Driven by Master)
FRAME/
(Driven by Master)
Master-Addr; Data)
Master-Addr; Data)
16 32
Data In
Byte Enable
Out
Data In
Lower
Address
Data In