LSI 53C875A - Manual (Page 279)

PCI and External Memory Interface Timing Diagrams 6-41
Figure 6.24 External Memory Write (Cont.)
MAD
(Addr driven by LSI53C875A;
Data driven by Memory)
11 12 13 14 15 16 17 18 19 20 21 10
CLK
(Driven by System)
PAR
(Driven by Master-Addr;
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C875A)
STOP/
(Driven by LSI53C875A)
DEVSEL/
(Driven by LSI53C875A)
AD
(Driven by Master-Addr;
C_BE[3:0]/
(Driven by Master)
FRAME/
(Driven by Master)
LSI53C875A-Data)
LSI53C875A-Data)
MAS1/
(Driven by LSI53C875A)
MAS0/
(Driven by LSI53C875A)
MWE/
(Driven by LSI53C875A)
MOE/
(Driven by LSI53C875A)
MCE/
(Driven by LSI53C875A)
In
Byte Enable
Lower
Address
t
2
t
1
t
2
t
2
t
3
t
3
t
24
Data In
t
2
t
25
t
20
t
26
t
21
t
22
t
23
9
Data Out