LSI 53C875A - Manual (Page 269)

PCI and External Memory Interface Timing Diagrams 6-31
Table 6.27 Burst Write, 32-Bit Address and Data
Symbol Parameter Min Max Unit
t
1
Shared signal input setup time 7 – ns
t
2
Shared signal input hold time 0 – ns
t
3
CLK to shared signal output valid 2 11 ns
t
10
CLK HIGH to GPIO1_MASTER/ HIGH – 20 ns