LSI 53C875A - Manual (Page 161)

SCSI Registers 4-69
Register: 0x39
DMA Interrupt Enable (DIEN)
Read/Write
R Reserved 7
MDPE Master Data Parity Error 6
BF Bus Fault 5
ABRT Aborted 4
SSI Single Step Interrupt 3
SIR SCRIPTS Interrupt Instruction Received 2
R Reserved 1
IID Illegal Instruction Detected 0
This register contains the interrupt mask bits corresponding to the
interrupting conditions described in the
DMA Status (DSTAT) register. An
interrupt is masked by clearing the appropriate mask bit. Masking an
interrupt prevents IRQ/ from being asserted for the corresponding
interrupt, but the status bit is still set in the DSTAT register. Masking an
interrupt does not prevent setting the
Interrupt Status Zero (ISTAT0) DIP.
All DMA interrupts are considered fatal, therefore SCRIPTS stops
running when this condition occurs, whether or not the interrupt is
masked. Setting a mask bit enables the assertion of IRQ/ for the
corresponding interrupt. (A masked nonfatal interrupt does not prevent
unmasked or fatal interrupts from getting through; interrupt stacking
begins when either the
Interrupt Status Zero (ISTAT0) SIP or DIP bit is
set.)
The IRQ/ output is latched. Once asserted, it will remain asserted until
the interrupt is cleared by reading the appropriate status register.
Masking an interrupt after the IRQ/ output is asserted does not cause
deassertion of IRQ/.
7 6 5 4 3 2 1 0
R MDPE BF ABRT SSI SIR R IID
x 0 0 0 0 0 x 0