Register: 0x4c – LSI 53C875A User Manual
Page 179
SCSI Registers
4-87
chip can arbitrate with only one ID value in the SCID
register.
Register: 0x4C
SCSI Test Zero (STEST0)
Read Only
SSAID
SCSI Selected As ID
[7:4]
These bits contain the encoded value of the SCSI ID that
the LSI53C875A is selected during a SCSI selection
phase. These bits work in conjunction with the
and
registers, which contain the allowable IDs that the
LSI53C875A can respond to. During a SCSI selection
phase, when a valid ID is put on the bus, and the
LSI53C875A responds to that ID, the ID that the chip was
selected as will be written into the SSAID[3:0] bits.
SLT
Selection Response Logic Test
3
This bit is set when the LSI53C875A is ready to be
selected or reselected. This does not take into account
the bus settle delay of 400 ns. This bit is used for
functional test and fault purposes.
ART
Arbitration Priority Encoder Test
2
This bit is always set when the LSI53C875A exhibits the
highest priority ID asserted on the SCSI bus during
arbitration. It is primarily used for chip level testing, but it
may be used during low level mode operation to
determine if the LSI53C875A won arbitration.
SOZ
SCSI Synchronous Offset Zero
1
This bit indicates that the current synchronous SREQ/,
SACK/ offset is zero. This bit is not latched and may
change at any time. It is used in low level synchronous
SCSI operations. When this bit is set, the LSI53C875A
functioning as an initiator, is waiting for the target to
request data transfers. If the LSI53C875A is a target,
then the initiator has sent the offset number of
acknowledges.
7
4
3
2
1
0
SSAID
SLT
ART
SOZ
SOM
x
x
x
x
0
x
1
1