Figure2.2 parity checking/generation, 12 dma fifo, Dma fifo – LSI 53C875A User Manual
Page 49: Parity checking/generation, Figure 2.2
SCSI Functional Description
2-27
Figure 2.2
Parity Checking/Generation
2.2.12 DMA FIFO
The DMA FIFO is 8 bytes wide by 118 transfers deep. The DMA FIFO is
illustrated in
. The default DMA FIFO size is 112 bytes to
assure compatibility with older products in the LSI53C8XX family.
The DMA FIFO size may be set to 944 bytes by setting the DMA FIFO
Size bit, bit 5, in the
register.
PCI Interface**
PCI Interface**
PCI Interface**
PCI Interface**
DMA FIFO*
(64 bits X 118)
DMA FIFO*
(64 bits X 118)
DMA FIFO*
(64 bits X 118)
DMA FIFO*
(64 bits X 118)
SODL Register*
SIDL Register*
SODL Register*
SCSI FIFO**
(8 or 16 bits x 31)
SCSI Interface**
SCSI Interface**
SODR Register*
SCSI Interface**
SCSI Interface**
** = Parity protected
* = No parity protection
Asynchronous
SCSI Send
Asynchronous
SCSI Receive
Synchronous
SCSI Send
Synchronous
SCSI Receive
X
X
X
X
X
S
S
G
G
X = Check parity
G = Generate 32-bit even PCI parity
S = Generate 8-bit odd SCSI parity