LSI 53C875A - Manual (Page 162)

4-70 Registers
For more information on interrupts, see Chapter 2, “Functional
Description” .
Register: 0x3A
Scratch Byte Register (SBR)
Read/Write
SBR Scratch Byte Register [7:0]
This is a general purpose register. Apart from CPU
access, only register Read/Write and Memory Moves into
this register alter its contents. The default value of this
register is zero. This register is called the DMA Watchdog
Timer on previous LSI53C8XX family products.
Register: 0x3B
DMA Control (DCNTL)
Read/Write
CLSE Cache Line Size Enable 7
Setting this bit enables the LSI53C875A to sense and
react to cache line boundaries set up by the
DMA Mode
(DMODE) or PCI Cache Line Size register, whichever
contains the smaller value. Clearing this bit disables the
cache line size logic and the LSI53C875A monitors the
cache line size using the DMODE register.
PFF Prefetch Flush 6
Setting this bit causes the prefetch unit to flush its
contents. The bit clears after the flush is complete.
PFEN Prefetch Enable 5
Setting this bit enables an 8-Dword SCRIPTS instruction
prefetch unit. The prefetch unit, when enabled, will fetch
8 Dwords of instructions and instruction operands in
bursts of 4 or 8 Dwords. Prefetching instructions allows
7 0
SBR
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
CLSE PFF PFEN SSM IRQM STD IRQD COM
0 0 0 0 0 0 0 0