Scsi bus data lines (sbdl) – LSI 53C875A User Manual
Page 190
4-98
Registers
Index Mode 1 (64TIMOD set) table entry format:
EN64TIBMV
Enable 64-Bit Table Indirect BMOV
1
Setting this bit enables 64-bit addressing for Table
Indirect BMOVs using the upper byte (bit [24:31]) of the
first Dword of the table entry. When this bit is cleared
table indirect BMOVs will use the
register to obtain the upper 32 bits of
the data address.
EN64DBMV
Enable 64-Bit Direct BMOV
0
Setting this bit enables the 64-bit version of a direct
BMOV. When this bit is cleared direct BMOVs will use the
Static Block Move Selector (SBMS)
register to obtain the
upper 32 bits of the data address.
Registers: 0x58–0x59
SCSI Bus Data Lines (SBDL)
Read Only
SBDL
SCSI Bus Data Lines
[15:0]
This register contains the SCSI data bus status. Even
though the SCSI data bus is active low, these bits are
active high. The signal status is not latched and is a true
representation of exactly what is on the data bus at the
time the register is read. This register is used when
receiving data using programmed I/O. This register can
also be used for diagnostic testing or in low level mode.
The power-up value of this register is indeterminate.
If the chip is in the wide mode (
, bit 3 and
, bit 2 are
set) and SBDL is read, both byte lanes are checked for
parity regardless of phase. When in a nondata phase,
this will cause a parity error interrupt to be generated
because the upper byte lane parity is invalid.
[31:24]
[23:0]
Src/Dest Addr [39:32]
Byte Count
Source/Destination Address [31:0]
15
0
SBDL
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x