LSI 53C875A - Manual (Page 93)

LSI53C875A PCI to Ultra SCSI Controller 4-1
Chapter 4
Registers
This chapter describes all LSI53C875A registers and is divided into the
following sections:
•
Section 4.1 “PCI Configuration Registers”
•
Section 4.2 “SCSI Registers”
•
Section 4.3 “64-Bit SCRIPTS Selectors”
•
Section 4.4 “Phase Mismatch Jump Registers”
In the register descriptions, the term “set” is used to refer to bits that are
programmed to a binary one. Similarly, the term “cleared” is used to refer
to bits that are programmed to a binary zero. Write any bits marked as
reserved to zero; mask all information read from them. Reserved bit
functions may change at any time. Unless otherwise indicated, all bits in
registers are active HIGH, that is, the feature is enabled by setting the
bit. The bottom row of every register diagram shows the default register
values, which are enabled after the chip is powered on or reset.
Reserved registers and bits are shaded in the register tables.
4.1 PCI Configuration Registers
The PCI Configuration registers are accessed by performing a
configuration read/write to the device with its IDSEL pin asserted and the
appropriate value in AD[10:8] during the address phase of the
transaction. The LSI53C875A responds to a binary value of 000b.
Table 4.1 describes the PCI configuration registers
All PCI-compliant devices must support the Vendor ID , Device ID ,
Command , and Status registers. Support of other PCI-compliant
registers is optional. In the LSI53C875A, registers that are not supported
are not writable and return all zeros when read. Only those registers and