LSI 53C875A - Manual (Page 72)

2-50 Functional Description
2.4 Serial EEPROM Interface
The LSI53C875A implements an interface that allows attachment of a
serial EEPROM device to the GPIO0 and GPIO1 pins. There are two
modes of operation relating to the serial EEPROM and the Subsystem
ID and Subsystem Vendor ID registers. These modes are programmable
through the MAD7 pin which is sampled at power-up.
2.4.1 Default Download Mode
In this mode, MAD7 is pulled down internally, GPIO0 is the serial data
signal (SDA) and GPIO1 is the serial clock signal (SCL). Certain data in
the serial EEPROM is automatically loaded into chip registers at
power-up.
The format of the serial EEPROM data is defined in Table 2.7 . If the
download is enabled and an EEPROM is not present, or the checksum
fails, the
Subsystem ID and Subsystem Vendor ID registers read back all
zeros. At power-up, only five bytes are loaded into the chip from locations
0xFB through 0xFF.
The Subsystem ID and Subsystem Vendor ID registers are read only, in
accordance with the PCI specification, with a default value of all zeros if
the download fails.